
MC68F375
SIGNAL DESCRIPTIONS
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
2-6
Table 2-5 Signal Functions
Signal Name
Mnemonic
Function
Address Bus
ADDR[23:0]
24-bit address bus used by CPU32
QADC64 Analog Input
AN[59:48]/[3:0]
Sixteen channel A/D converter analog input pins
QADC64 Analog Input
AN[z, y, x, w]
Four input channels utilized when operating in multiplexed mode
Analog MUX Inputs
ANX[15:0]
Analog signal inputs multiplexed to the analog converters
Address Strobe
AS
Indicates that a valid address is on the address bus
Autovector
AVEC
Requests an automatic vector during interrupt acknowledge
Bus Error
BERR
Indicates that a bus error has occurred
Bus Grant
BG
Indicates that the MCU has relinquished the bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Bus Request
BR
Indicates that an external device requires bus mastership
System Clock Out
CLKOUT
Internal system clock
TOUCAN Receive Data
CNRX
CAN 2.0B Serial Data Input
TOUCAN Transmit Data
CNTX
CAN 2.0B Serial Data Output
Chip Selects
CS[10:5], CS[3],
CS[0]
Select external devices at programmed addresses
Boot Chip Select
CSBOOT
Chip select for external boot start-up ROM
Emulator Chip Select
CSE
Chip select for external port emulator
Module Chip Select
CSM
Chip select for external ROM emulator
CTM PWM
CPWM[8:5]
PWM channels which can also be used as general-purpose output
pins
CTM9 Double Action
Channel
CTD[10:9]
Bidirectional CTM9 double action timer channels
CTM9 Modulus Clock
CTM2C
CTM9 modulus counter clock input
CTM9 Single Action Chan-
nels
CTS[20B - 14A]
Bidirectional CTM9 single action timer channels
Data Bus
DATA[15:0]
16-bit data bus
Data Strobe
DS
Read cycle — indicates that an external device should place valid
data on the data bus. Write cycle — indicates that valid data is on
the data bus.
Data and Size
Acknowledge
DSACK[1:0]
Provides asynchronous data transfers and dynamic bus sizing
Development Serial In, Out,
Clock
DSI, DSO, DSCLK
Serial I/O and clock for background debug mode
QADC64 External Trigger
ETRIG[2:1]
When a scan queue is in external trigger mode, the corresponding
ETRIG pin is configured as a digital input and the software pro-
grammed I/O direction in the DDR is ignored.
Crystal Oscillator
EXTAL, XTAL
Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
VCO Reference Mode Se-
lect
FASTREF
Selects between FAST or SLOW reference modes
Function Codes
FC[2:0]
Identify processor state and current address space
Freeze
FREEZE
Indicates that the CPU has acknowledged a breakpoint
Halt
HALT
Suspend external bus activity
Instruction Pipeline
IPIPE
Indicates instruction pipeline activity
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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