MC68F375
CAN 2.0B CONTROLLER MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
7-11
7.4.5 Time Stamp
The value of the free-running 16-bit timer is sampled at the beginning of the identifier
field on the CAN bus. For a message being received, the time stamp is stored in the
time stamp entry of the receive message buffer at the time the message is written into
that buffer. For a message being transmitted, the time stamp entry is written into the
transmit message buffer once the transmission has completed successfully.
The free-running timer can optionally be reset upon the reception of a frame into mes-
sage buffer 0. This feature allows network time synchronization to be performed.
7.5 TouCAN Operation
The basic operation of the TouCAN can be divided into three areas:
Reset and initialization of the module
Transmit message handling
Receive message handling
Example sequences for performing each of these processes is given in the following
paragraphs.
7.5.1 TouCAN Reset
The TouCAN can be reset in two ways:
Hard reset, using one of the IMB3 reset lines.
Soft reset, using the SOFTRST bit in the module configuration register.
Following the negation of reset, the TouCAN is not synchronized with the CAN bus,
and the HALT, FRZ, and FRZACK bits in the module configuration register are set. In
this state, the TouCAN does not initiate frame transmissions or receive any frames
from the CAN bus. The contents of the message buffers are not changed following
reset.
Any configuration change or initialization requires that the TouCAN be frozen by either
the assertion of the HALT bit in the module configuration register or by reset.
7.5.2 TouCAN Initialization
Initialization of the TouCAN includes the initial configuration of the message buffers
and configuration of the CAN communication parameters following a reset, as well as
any reconfiguration which may be required during operation. The following is a general
initialization sequence for the TouCAN:
1. Initialize all operation modes
a. Initialize the transmit and receive pin modes in control register 0
(CANCTRL0).
b. Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and
RJW in control registers 1 and 2 (CANCTRL[1:2]).
c. Select the S-clock rate by programming the PRESDIV register.
d. Select the internal arbitration mode (LBUF bit in CANCTRL1).
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Freescale Semiconductor, Inc.
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