MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-47
4POL
Output pin polarity control. The POL bit is a control bit that allows the software to set the polarity
of the PWM output signal. It works in conjunction with the EN bit and controls whether the
PWMSM drives the output pin with the true or inverted value of the output flip-flop, see Table 3EN
Enable control. The EN bit is a control bit that allows the software to enable and disable the
PWMSM as required.
0 = Disable the PWMSM and stop generation of PWM output pulses.
1 = Enable the PWMSM and start generation of PWM output pulses.
While the PWMSM is disabled (EN = 0):
– The output flip-flop is held reset and the level on the output pin is set to one or zero
according to the state of the POL bit,
– The PWMSM’s divide-by-256 prescaler is held in reset,
– The counter stops incrementing and is held equal to 0x0001,
– The comparators are disabled,
– And the PWMA1 and PWMB1 registers permanently transfer their contents to the buffer
registers (PWMA2 and PWMB2, respectively).
When the EN bit is changed from zero to one:
– The output flip-flop is set to start the first pulse,
– The PWMSM’s divide-by-256 prescaler is released,
– The counter is released and starts to increment from 0x0001,
– And the FLAG bit is set (to indicate that PWMA1 and PWMB1 can be updated with new
values of period and pulse width.
While EN is set, the PWMSM generates continuously a pulse width modulated output signal
based on the data in PWMA2 and PWMB2 (which are updated via PWMA1 and PWMB2 each
time a period is completed). To prevent unwanted glitches on the output waveform when dis-
abling the PWMSM, the EN bit should not be cleared by the software until one period has been
output as a 0% pulse (PWMB2 = 0x0000)
2:0
CLK[2:0]
Clock rate selection. The CLK bits are control bits that allow the software to select one of the
eight counter clock sources coming from the PWMSM prescaler. These bits can be changed by
the software at any time. Table 13-17 shows the counter clock sources and rates in detail.
Table 13-15 PWMSIC Bit Settings (Continued)
Bit(s)
Name
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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