
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-14
5.9.2 Front-End Analog Multiplexer
The internal multiplexer selects one of the 16 analog input pins or one of three special
internal reference channels for conversion. The following are the three special
channels:
VRH — Reference voltage high
VRL — Reference voltage low
(VRH – VRL)/2 — Mid-reference voltage
The selected input is connected to one side of the DAC capacitor array. The other side
of the DAC array is connected to the comparator input. The multiplexer also includes
positive and negative stress protection circuitry, which prevents other channels from
affecting the present conversion when excessive voltage levels are applied to the
cific voltage level limits.
5.9.3 Digital-to-Analog Converter Array
The digital-to-analog converter (DAC) array consists of binary-weighted capacitors
and a resistor-divider chain. The array serves two purposes:
The array holds the sampled input voltage during conversion.
The resistor-capacitor array provides the mechanism for the successive approx-
imation A/D conversion.
Resolution begins with the MSB and works down to the LSB. The switching sequence
is controlled by the SAR logic.
5.9.4 Comparator
The comparator is used during the approximation process to sense whether the digi-
tally selected arrangement of the DAC array produces a voltage level higher or lower
than the sampled input. The comparator output feeds into the SAR which accumulates
the A/D conversion result sequentially, starting with the MSB.
5.9.5 Successive Approximation Register
The input of the successive approximation register (SAR) is connected to the compar-
ator output. The SAR sequentially receives the conversion value one bit at a time,
starting with the MSB. After accumulating the ten bits of the conversion result, the SAR
data is transferred by the queue control logic in the digital section to the appropriate
result location, where it may be read by user software.
5.10 Digital Control Subsystem
The digital control subsystem includes the clock and periodic/interval timer, control
and status registers, the conversion command word table RAM, and the result word
table RAM.
The central element for control of QADC64 conversions is the 64-entry conversion
command word (CCW) table. Each CCW specifies the conversion of one input chan-
nel. Depending on the application, one or two queues can be established in the CCW
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Freescale Semiconductor, Inc.
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