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| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 93/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
67
4 Central Processing Unit
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher
performance while maintaining maximum compatibility with existing systems.
4.1 Overview
Ease of programming is an important consideration when using a microcontroller. The CPU16 instruc-
tion set is optimized for high performance. There are two 16-bit general-purpose accumulators and
three 16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load
and store operations, as well as 16- and 32-bit signed fractional operations. Code development is sim-
plified by the background debugging mode.
CPU16 memory space includes a 1-Mbyte data space and a 1-Mbyte program space. Twenty-bit ad-
dressing and transparent bank switching are used to implement extended memory. In addition, most
instructions automatically handle bank boundaries.
The CPU16 includes instructions and hardware to implement control-oriented digital signal processing
functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to mul-
tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu-
mulator. Modulo addressing supports finite impulse response filters.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. These languages make rapid development of portable software possible. The
CPU16 instruction set supports high-level languages.
4.2 M68HC11 Compatibility
CPU16 architecture is a superset of M68HC11 CPU architecture. All M68HC11 CPU resources are
available in the CPU16. M68HC11 CPU instructions are either directly implemented in the CPU16, or
have been replaced by instructions with an equivalent form. The instruction sets are source code com-
patible, but some instructions are executed differently in the CPU16. These instructions are mainly re-
lated to interrupt and exception processing — M68HC11 CPU code that processes interrupts, handles
stack frames, or manipulates the condition code register must be rewritten.
CPU16 execution times and number of cycles for all instructions are different from those of the
M68HC11 CPU. As a result, cycle-related delays and timed control routines may be affected.
The CPU16 also has several new or enhanced addressing modes. M68HC11 CPU direct mode ad-
dressing has been replaced by a special form of indexed addressing that uses the new IZ register and
a reset vector to provide greater flexibility.
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