參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 124/128頁
文件大小： 571K
代理商： MC16V1CPU20B1
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
95
5.3 Pin Function
Table 51 is a summary of the functions of the QSM pins when they are not configured for general-pur-
pose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an input or
output.
5.4 QSM Registers
QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI
submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate
sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unim-
plemented bits always return a logic zero value.
5.4.1 Global Registers
The QSM global registers contain system parameters used by both the QSPI and the SCI submodules.
These registers contain the bits and fields used to configure the QSM.
The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.
The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is
not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert-
ed. STOP can be negated by the CPU and by reset.
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
Table 51 QSM Pin Functions
Pin
Mode
Pin Function
MISO
Master
Serial Data Input to QSPI
Slave
Serial Data Output from QSPI
MOSI
Master
Serial Data Output from QSPI
Slave
Serial Data Input to QSPI
SCK
Master
Clock Output from QSPI
Slave
Clock Input to QSPI
PCS0/SS
Master
Input: Assertion Causes Mode Fault
Output: Selects Peripherals
Slave
Input: Selects the QSPI
PCS[3:1]
Master
Output: Selects Peripherals
Slave
None
TXD
Transmit
Serial Data Output from SCI
RXD
Receive
Serial Data Input to SCI
QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ1
FRZ0
0
SUPV
0
IARB[3:0]
RESET:
0
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