參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 81/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MOTOROLA
MC68HC16V1
56
MC68HC16V1TS/D
The port F edge detect flag register indicates when the proper transition has occurred on a port F pin
programmed for edge-detect I/O. A flag is set in this register any time the specified edge is detected on
a corresponding pin, regardless of whether the pin is configured as an input or output. If a pin is config-
ured as an interrupt request, bus error (BERR), or address latch enable (ALE), the flag for that pin is
not set on a transition. To clear flags in PORTFE, read the register and then write to the register with
zeros in the positions of the flags to be cleared.
Port F edge-detect I/O interrupt enable register bits are used to enable interrupts from individual edge-
detect I/O pins. If a bit is set to one, the specified edge on the corresponding pin generates an interrupt
request at the interrupt priority level specified by the PFEL[2:0] field of the port F interrupt level register.
If the bit is zero, the corresponding edge-detect I/O pin does not generate an interrupt request when an
edge is detected. In either case, the corresponding edge detect flag is set in the port F edge-detect flag
register.
Table 36 Port F Pin Assignments
PFPAR FIELD
Port F Signal
Primary Function
PFPA7
PF7
IRQ7
PFPA6
Reserved
PFPA5
Reserved
PFPA4
Reserved
PFPA3
Reserved
PFPA2
PF2
IRQ2
PFPA1
PF1
IRQX/BERR
PFPA0
PF0
ALE
Table 37 Port F Pin Assignment Register Field Encodings
MSB
LSB
Description
0
Edge-sensitive interrupt request input (I/O on PF0)
0
1
Rising edge-detect I/O pin
1
0
Falling edge-detect I/O pin
1
Level-sensitive interrupt request (I/O on PF0)
PORTFE — Port F Edge-Detect Flag Register
$YFFA39
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PFE7
RESERVED
PFE2
PFE1
PFE0
RESET:
0
PFEER — Port F Edge-Detect I/O Interrupt Enable Register
$YFFA3B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PFEE7
RESERVED
PFEE2
PFEE1
PFEE0
RESET:
0
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