參數(shù)資料
型號: MC16V1CPU20B1
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 73/128頁
文件大?。?/td> 571K
代理商: MC16V1CPU20B1
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
49
3.8.1 Port A and B Operation
Ports A and B can be configured as either input or output ports on a whole port basis. Depending on
the mode of the SLIM configured during reset, port A and port B can come out of reset as digital inputs
or as address bus pins.
Port A and B output data registers are used to latch the data to be driven on their respective port output
pins if port A or port B is configured as an output. When read, ports A and B output data registers always
reflect the current state of the data latches. Power-on reset can change the state of these latches. All
other sources of reset have no effect.
When read, pin data registers A and B reflect the current state of their respective pins, regardless of
whether the pins are configured as inputs or outputs. Writes have no effect.
Table 31 I/O Port Functions and Availability
Port
Primary Function
Availability
Single-Chip
Expanded
Non-Multiplexed
(16-Bit Data Bus)
Expanded
Non-Multiplexed
(8-Bit Data Bus)
Expanded
Multiplexed
A
ADDR/DATA[15:8]
X
B
ADDR/DATA[7:0]
X
C
ADDR[17:16]
X
D
Chip-selects, background debug
mode
XX
X
E
Bus control
X
F
Interrupts, bus control
X
G
DATA[15:8]
X
X
H
DATA[7:0]
X
X
PORTA — Port A Output Data Register
$YFFA10
PORTB — Port B Output Data Register
$YFFA11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
U
PORTAP — Port A Pin Data Register
$YFFA12
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAP7
PAP6
PAP5
PAP4
PAP3
PAP2
PAP1
PAP0
PORTBP
RESET:
CURRENT STATE OF CORRESPONDING PINS
PORTBP — Port B Pin Data Register
$YFFA13
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PORTAP
PBP7
PBP6
PBP5
PBP4
PBP3
PBP2
PBP1
PBP0
RESET:
CURRENT STATE OF CORRESPONDING PINS
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