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參數(shù)資料
| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 69/128頁 |
| 文件大小： | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
45
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy-
cles. At the end of this 10-cycle period, the RESET input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the RESET input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-
impedance state for 10 cycles, then it is tested again. The process repeats until RESET is released.
3.6.5 Power-On Reset
When the SLIM clock synthesizer is used to generate system clocks, power-on reset involves special
circumstances related to application of system and clock synthesizer power. When fast or slow refer-
ence mode is selected, voltage must be applied to the clock synthesizer power input pin (VDDSYN) for
the MCU to operate. The following discussion assumes that, to minimize crystal start-up time, VDDSYN
is applied before and during reset. When VDDSYN is applied at power-on, start-up time is affected by
specific crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state dur-
ing reset.
During power-on reset, an internal circuit in the SLIM drives the IMB internal and external RESET lines.
The circuit releases the internal RESET line as VDD ramps up to the minimum specified value, and SLIM
pins are initialized. When VDD reaches minimum value, the clock synthesizer VCO begins operation,
and clock frequency ramps up to limp mode frequency. The external RESET signal remains asserted
until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SLIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal RESET signal is asserted for four clock cycles, these modules reset. VDD ramp time
and VCO frequency ramp time determine how long the four cycles take. Worst case is approximately
15 milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-
ers or isolation resistors to prevent conflict.
3.6.6 Use of Three-State Control
When the three state control (TSC) input is asserted simultaneously with the RESET pin, the MCU plac-
es all output drivers in an inactive, high-impedance state. The signal must remain asserted for 10 clock
cycles for drivers to change state.
When using TSC during power-up reset, note the following constraints:
When the internal PLL clock synthesizer is used, synthesizer ramp-up time affects how long the
10 cycles take. Worst case is approximately 20 milliseconds from TSC assertion.
When an external clock signal is applied, pins go to a high-impedance state as soon as 10 clock
pulses have been applied to the EXTAL pin after TSC assertion.
NOTE
When TSC assertion takes effect, internal signals are forced to values that can
cause inadvertent mode selection. Once the output drivers change state, the MCU
must be powered down and restarted before normal operation can resume.
3.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
SLIM, and a device or module requesting interrupt service.
The CPU16 provides for seven levels of interrupt priority (1–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the in-
terrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asyn-
chronous exception.
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