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| 型號(hào)： | MC16V1CPU20B1 |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 2/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
10
MC68HC16V1TS/D
2.5 MC68HC16V1 Signal Function
Table 6 MCU Signal Function
Signal Name
Mnemonic
Function
Address Bus
ADDR[17:0]
18-bit address used by CPU16
Address Latch Enable
ALE
Enables external address latching by indicating when address is
valid on address/data bus
Address Strobe
AS
Indicates that a valid address is on the address bus
Bus Error
BERR
Signals to the SLIM that a bus error has occurred
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Clock Out
CLKOUT
System clock output
Chip Selects
CSA, CSB, CSC
Select external devices at programmed addresses. CSB can ad-
dress boot memory at reset
Data Bus
DATA[15:0]
16-bit data bus
Data Strobe
DS
Indicates that an external device should place valid data on the
data bus during a read cycle and that valid data has been placed
on the bus by the CPU during a write cycle
Data Transfer
Acknowledge
DTACK
Acknowledges to the SLIM that data has been received for a write
cycle, or that data is valid on the data bus for a read cycle
Development Serial I/O,
Clock
DSI, DSO,
DSCLK
Serial I/O for background debug mode and clock for background
debug mode
Drive Reset Configuration
Data
DRCD
Causes the MCU to take configuration information from inputs to
the SLIM during reset instead of from the MCRC and PCON regis-
ters
Crystal Oscillator
EXTAL, XTAL
Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
External Bus Request
EBR
Prevents MCU from being able to use external bus
External Filter Capacitor
XFC
Connection for external phase-locked loop filter capacitor
Freeze
FREEZE
Indicates that the CPU16 has entered background mode
Function Codes
FC[2:0]
Identifies processor state and current address space
Programmable Interrupt
Request Level
IRQX
Provides a programmable interrupt priority level to the CPU; can
also be configured as bus error input indication
Input Capture Inputs
IC[3:1]
GPT input capture inputs
Interrupt Request Inputs
IRQ7, IRQ2
Request interrupt service from CPU16
Instruction Pipeline
IPIPE[1:0]
Indicates instruction pipeline activity
Master In Slave Out
MISO
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Master Out Slave In
MOSI
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Peripheral Chip-Selects
PCS[3:0]
QSPI peripheral chip selects
Port A
PA[7:0]
Port A digital input or output signals
Port B
PB[7:0]
Port B digital input or output signals
Port C
PC[1:0]
Port C digital input or output signals
Port D
PD[7:0]
Port D digital input or output signals
Port E
PE[7:0]
Port E digital input or output signals
Port F
PF7, PF[2:0]
Port F digital input or output signals
Port G
PG[7:0]
Port G digital input or output signals
Port GP
PGP[7:0]
GPT digital input or output signals
Port H
PH[7:0]
Port H digital input or output signals
Port QS
PQS[7:0]
QSM digital input or output signals
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