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參數資料
| 型號： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 60/128頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
37
3.5.2 Function Codes
Function code signals (FC[2:0]) are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 through
3 are not used. Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 19 is a summary of the function code assignments.
3.5.3 Address Bus
Address bus signals (ADDR[17:0]) define the address of the most significant byte to be transferred dur-
ing a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address
is valid while AS is asserted.
3.5.4 Address Strobe
Address strobe (AS) is a timing signal that indicates the validity of an address on the address bus and
the validity of many control signals. It is asserted one-half clock after the beginning of a bus cycle. In
multiplexed mode, a valid address is qualified by the ALE signal.
3.5.5 Data Bus
In non-multiplexed modes, data bus signals DATA[15:0] comprise a bidirectional parallel bus that trans-
fers data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle.
During a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus
cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand
size. The MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
In multiplexed mode, the 16-bit address/data bus contains valid addresses whenever address latch en-
able (ALE) is asserted. After ALE is negated, DS is asserted and data is transferred to or from the MCU.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.5.7 Address Latch Enable
In multiplexed mode, address latch enable (ALE) denotes a valid address on the ADDR/DATA[15:0]
bus. ALE asserts during the high time of the first CLKOUT cycle of each multiplexed bus access, and
negates during the CLKOUT low time that immediately follows. Figure 10 shows an example of how to
demultiplex the address/data bus using ALE.
Table 19 CPU16 Address Space Encoding
FC2
FC1
FC0
Address Space
1
0
Reserved
1
0
1
Data Space
1
0
Program Space
1
CPU Space
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