參數(shù)資料
型號(hào): MC16V1CPU20B1
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 50/128頁
文件大?。?/td> 571K
代理商: MC16V1CPU20B1
MOTOROLA
MC68HC16V1
28
MC68HC16V1TS/D
Figure 9 Software Watchdog, Real-Time Clock and Prescaler
The system protection control register controls system monitor functions such as the halt monitor, the
software watchdog, and the bus monitor.
REN — Real-Time Reset Enable
This bit controls whether writes to the RTP register reset the prescaler.
0 = Prescaler not reset when writing to RTP.
1 = Prescaler reset when writing to RTP.
SREN — Software Watchdog Reset Enable
This bit controls whether writes to the SWP register reset the prescaler.
0 = Prescaler not reset when writing to the SWP.
1 = Prescaler reset when writing to the SWP.
PCLK — Prescaler Clock Select
This bit selects the clock source to the prescaler.
0 = Selects system clock output divided by two (fsys ÷ 2).
1 = Selects clock synthesizer reference input divided by two (fref ÷ 2).
SYPCR — System Protection Control Register
$YFFA50
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
REN
SREN
PCLK
SLPC
RZ
SZ
IRSEL
TIEN
0
TIQL[2:0]
HME
BME
BMT[1:0]
RESET:
0
REAL-TIME DOWNCOUNTER
RTP (READABLE)
RZ STATUS
FLAG
ENABLE
TIEN
TIMER
SLIM SYS PROT TIMER
SREN
WRITE SWP
WRITE RTP
REN
PRR
RTC PRESCALER/CLOCK MUX
SW PRESCALER/CLOCK MUX
SW DOWNCOUNTER
SWP (READABLE)
SZ STATUS
FLAG
SELECT
IRSEL
RESET
TIMER
RTCLK
SWCLK
CLOCK
PRESCALER (READABLE)
CLOCK
SELECT
MUX
FREEZE
RESET
PRESCALER
÷ 16
PRESCALER
÷ 64
PRESCALER
÷ 256
PRESCALER
÷ 1024
210 28
24
26
INTERRUPT
SYNTHESIZER
f ref
÷2
f sys
÷2
PCLK
SYSPROT
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