參數(shù)資料
型號: MC16V1CPU20B1
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 75/128頁
文件大?。?/td> 571K
代理商: MC16V1CPU20B1
MOTOROLA
MC68HC16V1
50
MC68HC16V1TS/D
Port A and B data direction registers control the direction of the pin drivers for ports A and B, respec-
tively, when the pins are configured for I/O. Setting DDA or DDB to one configures all pins in the corre-
sponding port as outputs. Clearing DDA or DDB to zero configures all pins in the corresponding port as
inputs.
3.8.2 Port C Operations
Port C pins can be used as address lines or general purpose I/O. ADDR[17:16] are selected in a single
contiguous left-justified group, to form a contiguous address space with DATA[15:0].
The port C output data register latches the data to be driven on the port C output pins. When read,
PORTC always reflects the current state of the data latches. Power-on reset can change the state of
these latches. Other sources of reset have no effect.
When read, the port C pin data register reflects the current state of the port C pins, regardless of wheth-
er the pins are configured as inputs or outputs. Writes to PORTCP have no effect.
Port C data direction register bits control the direction of the port C pin drivers when the pins are con-
figured as I/O pins. When any bit in this register is set to one, the corresponding pin is configured as an
output. When any bit in this register is cleared to zero, the corresponding pin is configured as an input.
Reset clears all bits to zero.
DDRAB — Port A/B Data Direction Register
$YFFA15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
DDA
DDB
RESET (SINGLE-CHIP MODE):
0
PORTC — Port C Output Data Register
$YFFA18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PC1
PC0
PORTD
RESET:
U
PORTCP — Port C Pin Data Register
$YFFA1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PCP1
PCP0
PORTDP
RESET:
CURRENT STATE OF CORRESPONDING PINS
DDRC — Port C Data Direction Register
$YFFA1C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DDC1
DDC0
DDRD
RESET:
0
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