參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 90/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MOTOROLA
MC68HC16V1
64
MC68HC16V1TS/D
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected
1 = Synchronous mode selected
In asynchronous mode, the chip-select is asserted synchronized with AS or DS. In synchronous mode,
the chip select is asserted synchronized with the optional ECLK pin. Although the MC68HC16V1 does
not have ECLK, synchronous mode bus accesses can still be performed.
The DTACK[3:0] field is not used in synchronous mode because a bus cycle is only performed as an
asynchronous operation. When a match condition occurs on a chip-select programmed for synchronous
operation, the chip select signals the EBI that an E-clock cycle is pending.
BYTE[1:0] — Upper/Lower Byte Option
This field is used to control the assertion of chip selects configured for 16-bit port accesses. Chip selects
configured for 8-bit port accesses should use the BYTE = %11 (both bytes) encoding. BYTE = %00 dis-
ables the specified chip select. Table 41 lists upper/lower byte options.
R/W[1:0] — Read/Write
This field causes a chip select to be asserted only for read, only for write, or for both read and write
cycles. R/W = %00 disables the specified chip-select. Refer to Table 42.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with AS. Selecting data strobe causes chip se-
lect to be asserted synchronized with DS.
DTACK[3:0] — Data Transfer Acknowledge
This field specifies the source of DTACK in asynchronous mode. Bus timing can be adjusted with inter-
nal DTACK generation by controlling the number of wait states that are inserted in a bus cycle. Table
43 shows the DTACK field encoding.
Table 41 Upper/Lower Byte Options
BYTE[1:0]
Description
00
Disable
01
Lower Byte
10
Upper Byte
11
Both Bytes
Table 42 R/W Encoding
R/W[1:0]
Description
00
Disable
01
Read Only
10
Write Only
11
Read/Write
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