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參數(shù)資料
| 型號： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 70/128頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
46
MC68HC16V1TS/D
Interrupt recognition is based on the states of the IRQ7, IRQ2, IRQX, and the IP mask value set in the
CPU16 condition code register (CCR). Each of the signals corresponds to an interrupt priority. IRQ2
has the lowest priority, IRQ7 has the highest priority. IRQX has a user-definable priority based on the
setting of the IRQXL[2:0] bits in PFLVR. Refer to 3.8.5 Port F Operation for more information on the
port F interrupt level register (PFLVR).
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.
Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7)
from being recognized and processed. When IP contains %000, no interrupt is masked. During excep-
tion processing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by means of a wired NOR. Simultaneous requests of differing priority can
be made. Internal assertion of an interrupt request signal does not affect the logic state of the corre-
sponding MCU pin.
External interrupt requests are routed to the CPU16 via the external bus interface and SLIM interrupt
control logic. The CPU treats external interrupt requests as though they come from the SLIM.
IRQ7, IRQ2, and IRQX can be configured as active-low level-sensitive or edge detect inputs. They may
also be configured as general-purpose I/O pins, or edge detect pins, in which case they exist but do not
support the IRQ function. Control bits in the port F pin assignment register are used to assign the func-
tion. Refer to 3.8.5 Port F Operation for more information.
IRQ7 is a non-maskable interrupt that is input transition sensitive in order to prevent redundant servicing
and stack overflow. A non-maskable interrupt is generated each time IRQ7 is asserted, and each time
the priority mask changes from %111 to a lower number while IRQ7 is asserted.
IRQ2 and IRQX are maskable interrupts. IRQ2 asserts fixed interrupt priority level 2. IRQX can assert
any interrupt priority level as configured in the port F priority level register (PFLVR). Refer to 3.8.5 Port
F Operation for more information.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re-
quests are processed at instruction boundaries or when exception processing of higher-priority excep-
tions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
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