參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 53/128頁
文件大小： 571K
代理商： MC16V1CPU20B1
MOTOROLA
MC68HC16V1
30
MC68HC16V1TS/D
After reset, bus monitor timeout value defaults to 64 system clocks.
NOTE
For external accesses, this time-out value should be longer than the chip-select
access time.
3.4.1 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DTACK). The monitor asserts the internal BERR signal if response time is excessive.
DTACK response time is measured in clock cycles. The maximum allowable response time can be se-
lected by setting BMT[1:0].
The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. The monitor
does not check DTACK response on the external bus unless the CPU16 initiates the bus cycle. If a sys-
tem contains external bus masters, an external bus monitor must be implemented and the internal to
external bus monitor option must be disabled.
3.4.2 Spurious Interrupt Monitor
The spurious interrupt monitor issues internal BERR if no interrupt arbitration occurs during an IACK
cycle. Leaving IARB[3:0] set to %0000 in the module configuration register of any peripheral that can
generate interrupts will cause a spurious interrupt. Refer to Table 49 for the CPU16 interrupt vector ta-
ble.
3.4.3 Halt Monitor
The halt monitor responds to an assertion of the HALT signal on the internal bus caused by a double
bus fault. This signal is asserted by the CPU16 after a double bus fault occurs. If the HME bit is set to
one, the halt monitor is enabled, and asserts RESET when the HALT signal is asserted. A flag in the
reset status register (RSR) indicates that the last reset was caused by the halt monitor. The halt monitor
reset can be inhibited by clearing the HME bit in SYPCR.
3.4.4 Timer Control
The timer control register selects the time base for the real-time clock and software watchdog. It also
sets the vector used when these timers generate interrupts.
Table 13 Bus Monitor Timeout Period
BMT[1:0]
Timeout
0 0
64 System Clocks
0 1
32 System Clocks
1 0
16 System Clocks
1 1
8 System Clocks
TIC — Timer Control Register
$YFFA52
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRR
SWC[2:0]
0
RTC[2:0]
TIV[7:0]
RESET:
0
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