- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45204 > MC16V1CPU20B1 (MOTOROLA INC) 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 71/128頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
47
3.7.1 Interrupt Acknowledge Cycle
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 de-
tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to
mask lower-priority interrupts during exception processing, and it is decoded by modules that have re-
quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to
them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of
serial contention between module interrupt arbitration (IARB) field values.
Each module that can make an interrupt service request, including the SLIM, has an IARB field in its
module configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to
%1111 (highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious
interrupt exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SLIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SLIM is %1111, and the
reset IARB value for all other modules is %0000. Initialization software must assign different IARB val-
ues to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same non-zero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SLIM
wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by
a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not re-
spond in time, a spurious interrupt exception is taken.
3.7.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3.
Request priority is latched into the CCR IP field from the address bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC2670L | DOT MAT LCD DRVR AND DSPL CTLR, CDIP28 |
| MC2670P | DOT MAT LCD DRVR AND DSPL CTLR, PDIP28 |
| MC2671AS | 1 CHANNEL(S), SERIAL COMM CONTROLLER, CDIP40 |
| MC2671AL | 1 CHANNEL(S), SERIAL COMM CONTROLLER, CDIP40 |
| MC2675B5S | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC16XSD200FK | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual 16 mOhm High Side Switch |
| MC16Z1CFC25B1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC16Z1CPV20B1 | 制造商:Rochester Electronics LLC 功能描述:16 BIT MCU, 1K RAM - Bulk |
| MC16Z3BCAG16 | 功能描述:16位微控制器 - MCU 16BIT MCU 4KRAM 8KROM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MC-17 | 功能描述:TERM BARRIER 17CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標(biāo)準(zhǔn)包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點(diǎn):法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對(duì)苯二甲酸丁二酯（PBT），玻璃纖維增強(qiáng)型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。