參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 39/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MOTOROLA
MC68HC16V1
18
MC68HC16V1TS/D
PCON[13:11] — Port C[1:0] Default Configuration
This bit field selects the number of pins in PC[1:0] which come out of reset configured as address lines.
The address lines selected form a contiguous address space with ADDR[15:0]. The remaining pins in
PC[1:0] come out of reset as digital output pins. The default reset value in PCON[13:11] is overridden
if the SLIM comes out of reset in single chip mode. In this case, PC[1:0] are configured as digital inputs.
PCON[10:5] — Port D[7:5] Default Configuration
PCON10, PCON8, and PCON6 determine if CSA, CSB, and CSC are configured as chip-selects or dig-
ital I/O in the corresponding fields of PDPAR.
PCON9, PCON7, and PCON5 determine the port width if the associated chip-select is enabled.
PCON4 — Port D4 Default Configuration
This bit contains the default reset value of PDPAR4 to select the DTACK/PD4 pin as DTACK or digital
I/O out of reset.
PCON3 — Port E[7:5] Default Configuration
This bit controls whether PE[7:5] are configured as the three function code pins (FC[2:0]) or digital I/O
pins.
0 = Pins configured as PE[7:5]
1 = Pins configured as FC[2:0]
1. Certain PCON bit combinations are reserved in this SLIM implementation and should remain set to zero.
Table 10 Port/Clock Configuration Shadow Register (PCON)
Bit(s)1
States
Register
Pin(s) Affected
Selected Function
PCON[15:14]
0 0
NOT USED
PCON[13:11]
0 0 0
0 0 1
0 1 0
0 1 1
1 X X
PCPAR[2:0]
ADDR[17:16]/PC[1:0]
PC[1:0]
PC1, ADDR16
ADDR[17:16]
Reserved
PCON10
1
0
PDPAR7
CSA/PD7
CSA
PD7
PCON9
1
0
CSCR5
PH[7:0]
CSA = 16-Bit Port
CSA = 8-Bit Port
PCON8
1
0
PDPAR6
CSB/PD6
CSB
PD6
PCON7
1
0
CSCR4
PH[7:0]
CSB = 16-Bit Port
CSB = 8-Bit Port
PCON6
1
0
PDPAR5
CSC/PD5
CSC
PD5
PCON5
1
0
CSCR3
PH[7:0]
CSC = 16-Bit Port
CSC = 8-Bit Port
PCON4
1
0
PDPAR4
DTACK/PD4
DTACK
PD4
PCON3
1
0
PEPAR[7:5]
FC[2:0]/PE[7:5]
FC[2:0]
PE[7:5]
PCON2
1
0
SYNCR[15, 13:12]
NONE
System Clock = 2 X Reference
System Clock = 1 X Reference
PCON1
1
0
PEPAR4
CLKOUT/PE4
CLKOUT
PE4
PCON0
1
0
—
NONE
Slow Reference Mode
Fast Reference Mode
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