參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 82/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
57
The port F interrupt level register controls the interrupt levels requested by the IRQX programmable pri-
ority interrupt and the port F edge-detect I/O interrupts. Reads of PFLVR7 and PFLVR3 always return
zero; writes have not effect.
IRQXL[2:0] — IRQX Level
This field determines the interrupt level and function of the IRQX/BERR pin. When IRQXL[2:0] = %000,
the IRQX/BERR pin functions as the bus error input. When set to any non-zero value, the pin functions
as an interrupt request with the specified priority level. IRQX/BERR comes out of reset configured to
function as an interrupt request of priority level 1.
PFEL[2:0] — Port F Edge-Detect I/O Interrupt Level
This field specifies the priority level of port F edge-detect I/O interrupts; PFEL[2:0] = %000 disables
these interrupts. Whenever all SLIM interrupt sources are contending for the same priority level, port F
edge-detect interrupts have the lowest arbitration priority.
The port F edge-detect I/O interrupt vector register determines which vector in the exception vector ta-
ble is used for interrupts generated by the port F edge-detect logic.
3.8.6 Port G and H Operation
Ports G and H can be used as input/output ports when the SLIM is configured in expanded multiplexed
mode. In addition, port H may be used for digital I/O pin in expanded non-multiplexed mode if all of the
chip-select port size bits in the chip-select control register (CSCR) are configured for 8-bit data bus op-
eration.
Ports G and H can be configured as data bus pins or discrete I/O, depending on the mode of the SLIM
configured during reset.
The port G output data register latches the data to be driven on the port G output pins. When read, this
register always reflects the current state of the data latches. Power-on reset can change the state of
these latches. All other sources of reset have no effect.
PFLVR — Port F Interrupt Level Register
$YFFA3C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQXL[2:0]
0
PFEL[2:0]
PFIVR
RESET:
0
1
0
PFIVR — Port F Edge-Detect I/O Interrupt Vector Register
$YFFA3D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PFLVR
PFIVR
RESET:
0
1
PORTG — Port G Output Data Register
$YFFA28
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PORTH
RESET:
U
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