參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 27/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MOTOROLA
MC68HC16V1
122
MC68HC16V1TS/D
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumulation.
TIC[1:3] — Input Capture Registers 1–3
$YFF90E, $YFF910, $YFF912
The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT
when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF.
TOC[1:4] — Output Compare Registers 1–4
$YFF914, $YFF916, $YFF918, $YFF91A
The output compare registers are 16-bit read/write registers which can be used as output waveform
controls or as elapsed time indicators. For output compare functions, they are written to a desired match
value and compared against TCNT to control specified pin actions. They are reset to $FFFF.
TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, depending on the
state of I4/O5 in PACTL. It is reset to $FFFF.
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input
capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful. Refer to Table
EDG[4:1]B/A — Input Capture Edge Control Bits
Each pair of bits configures input sensing logic for the corresponding input capture. Refer to Table 65.
TCTL1/TCTL2 — Timer Control Registers 1–2
$YFF91E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A
RESET:
0
Table 64 OM/OL[5:2] Bit Field Effects
OM/OL[5:2]
Action Taken
00
Timer disconnected from output logic
01
Toggle OCx output line
10
Clear OCx output line to zero
11
Set OCx output line to one
Table 65 EDG[4:1]B/A Bit Field Effects
EDG[4:1]B/A
Configuration
00
Capture disabled
01
Capture on rising edge only
10
Capture on falling edge only
11
Capture on any (rising or falling) edge
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