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參數資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 96/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 84 of 112
ADDITIONAL RESTRICTIONS IN SLAVE MODE
When operating in slave mode, note the following restrictions:
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within one cycle prior to the VD falling edge.
If possible, all start-up serial writes should be performed
with VD and HD disabled. This prevents unknown
behavior caused by partial updating of registers before all
information is loaded. See the Power-Up Sequence for
Master Mode section.
There is an inhibit area for SHPLOC to meet the timing
This restriction is necessary to guarantee a stable reset of
the H-counter in slave mode.
When operating the part in slave mode and using a crystal
oscillator to generate CLI, it can be very difficult to meet
the tHDCLI specification because there is no phase control
over the oscillator output. Special care must be taken to
meet the critical tHDCLI specification when operating in this
condition.
VD
HD
CLI
XX
X
XX
X
XX
X
XX
X
tCLIDLY
06
87
8-
1
05
35.5 CYCLES
XX
X
0
X
XX
X
XX
X
12
H-COUNTER
RESET
SHPLOC
INTERNAL
HD
INTERNAL
H-COUNTER
(PIXEL COUNTER)
tVDHD
SHDLOC
INTERNAL
tHDCLI
tCLISHP
tSHPINH
tCONV
NOTES:
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED BY SHPLOC (INTERNAL SAMPLING EDGE).
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE AT SHDLOC (INTERNAL SAMPLING EDGE).
3. DEPENDING ON THE VALUE OF SHPLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 32, SHDLOC = 0 IS SHOWN. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH THE VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER THE VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN ONE CYCLE IMMEDIATELY BEFORE THE VD FALLING EDGE.
Figure 105. External VD/HD and Internal H-Counter Synchronization, Slave Mode
06
87
8-
1
06
1HBLKTOG1
60
(60 – 36) = 24
2HBLKTOG2
100
(100 – 36) = 64
3CLPOBTOG1
103
(103 – 36) = 67
4CLPOBTOG2
112
(112 – 36) = 76
MASTER MODE
SLAVE MODE
H1
CLPOB
PIXEL NO.
HD
112
103
100
60
0
1
2
3
4
Figure 106. Example of Slave Mode Register Settings to Obtain Desired Toggle Positions
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