- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 29 of 112
Increasing H-Clock Width During HBLK
The AD9920A allows the H1 to H8 pulse width to be increased
during the HBLK interval. As shown in Figure 36, the H-clock fre-
quency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12,
and so on, up to 1/30. To enable this feature, the HCLK_WIDTH
register (Address 0x35, Bits[7:4]) is set to a value between 1 and 15.
When this register is set to 0, the wide HCLK feature is disabled.
The reduced frequency occurs for only the H1 to H8 pulses that
are located within the HBLK area.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
HBLK Mode 1 Operation
HBLK Mode 1 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced from
one another are needed, HBLK Mode 1 can be used. Using a
separate set of registers, HBLK Mode 1 can divide the HBLK
region into up to six repeat areas (see Table 12).
As shown in Figure 37, each repeat area shares a common
group of toggle positions: HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC. However, the number of toggles following a start
position can be unique in each repeat area by using the RAxH1REP
and RAxH2REP registers; these registers, depending on the mode
of operation, are stored in the HBLKTOGO1 to HBLKTOGO6
and HBLKTOGE1 to HBLKTOGE6 registers (Address 0x19 to
Address 0x1E; see Table 63).
Table 13. HCLK Width Register
Register
Length (Bits)
Description
HCLK_WIDTH
4
Controls the H1 to H8 pulse widths during HBLK as a fraction of pixel rate
0 = same frequency as pixel rate; 1 = 1/2 pixel frequency (doubles the HCLK pulse width);
2 = 1/4 pixel frequency; 3 = 1/6 pixel frequency; 4 = 1/8 pixel frequency;
5 = 1/10 pixel frequency; 15 = 1/30 pixel frequency
HBLK
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLK_WIDTH REGISTER.
H1/H3
H2/H4
1/fPIX
2 × (1/fPIX)
06
87
8-
0
35
Figure 36. Generating Wide H-Clock Pulses During HBLK Interval
H1
H2
HBLKSTART
A
HBLKEND
REPEAT AREA 0
HD
B
C
REPEAT AREA 1
REPEAT AREA 2
REPEAT AREA 3
REPEAT AREA 4
REPEAT AREA 5
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RAxHxREPx = 0
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RAxHxREPx REGISTERS
CREATE UP TO THREE GROUPS OF TOGGLES
(A, B, C) COMMON IN ALL REPEAT AREAS
06
87
8-
0
36
Figure 37. HBLK Mode 1 Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。