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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 44 of 112
Sequence Line Alternation
To support the timing requirements of some advanced CCDs
in a memory-efficient manner, the AD9920A can automatically
increment the sequence number at the end of a given line through
the use of the SEQ_ALT_INC register (V-Sequence Register 0x09,
Bit 20). It can also reset the sequence number to the sequence
defined in the field register through the SEQ_ALT_RST register
(V-Sequence Register 0x09, Bit 21). Combining these two registers
allows the user to create a loop of sequences for a given region.
See Figure 56 for an example of how to use these two functions
together. The example in Figure 56 uses the register settings
listed in Table 18.
With these settings, at Sequence Change Position 0 (SCP0),
the AD9920A steps into Sequence 2. Because the Sequence 2
SEQ_ALT_INC = 1 and the SEQ_ALT_RST = 0, at the end of
that line the sequence number automatically increments to
Sequence 3. In the same way, at the end of that line, the
sequence number automatically increments to Sequence 4.
Because SEQ_ALT_INC = 0 and SEQ_ALT_RST = 1 for
Sequence 4, the AD9920A automatically resets the sequence
number to the sequence defined for that region in the field register,
which in this case is Sequence 2. The AD9920A continues to loop
in this fashion between Sequence 2, Sequence 3, and Sequence 4
until it reaches the next sequence change position.
It is important to note that the sequence number can increment
only at the end of a line and cannot be used to create more complex
patterns within one line. This is distinctly different from the special
vertical sequence alternation mode, which allows the user to
concatenate multiple sequences within one line (see the Special
Table 18. Register Settings for the Example in Figure 56
Field Registers
Sequence 2 Registers
Sequence 3 Registers
Sequence 4 Registers
Sequence 6 Registers
SCP0 = 0, SEQ0 = 2
SEQ_ALT_INC = 1
SEQ_ALT_INC = 0
SCP1 = 6, SEQ1 = 6
SEQ_ALT_RST = 0
SEQ_ALT_RST = 1
SEQ_ALT_RST = 0
VD
HD
SCP1
ACTIVE
SEQUENCE #
234
2
3
4
6
SCP0
068
78
-05
5
Figure 56. Example Output Using SEQ_ALT_INC and SEQ_ALT_RST Functions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
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