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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 60/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 51 of 112
VERTICAL TIMING EXAMPLE
To better understand how the AD9920A vertical timing genera-
tion is used, consider the example CCD timing chart in Figure 64.
This example illustrates a CCD using a general three-field read-
out technique. As shown in Figure 64, each readout field must be
The sequence change positions (SCPs) determine the line bound-
aries for each region, and the SEQ registers assign a particular
V-sequence to each region. The V-sequences contain the specific
timing information required in each region: V1 to V6 pulses
(using V-pattern groups), HBLK/CLPOB timing, and VSG
patterns for the SG active lines.
This timing example requires four regions for each of the three
fields, labeled Region 0, Region 1, Region 2, and Region 3. Because
the AD9920A allows many individual fields to be programmed,
FIELD1, FIELD2, and FIELD3 can be used to meet the require-
ments of this timing example. The four regions for each field are
very similar in this example, but the individual registers for each
field allow flexibility to accommodate other timing charts.
Region 0 is a high speed, vertical shift region. Sweep mode can be
used to generate this timing operation with the desired number
of high speed vertical pulses needed to clear any charge from
the CCD vertical registers.
Region 1 consists of only two lines and uses standard single-line
vertical shift timing. The timing of this region area is the same
as the timing in Region 3.
Region 2 is the sensor gate line in which the VSG pulses transfer
the image into the vertical CCD registers. This region may require
the use of the second V-pattern group for the SG active line.
Region 3 also uses the standard single-line vertical shift timing,
the same timing as Region 1. Four regions are required in each
of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers must be used during the actual readout operation.
These include the mode registers, shutter control registers
(PRIMARY_ACTION, SUBCK, and GPO for MSHUT and
VSUB control), and AFE gain registers.
Important Note Regarding Signal Polarities
When programming the AD9920A to generate the V1 to V24
and SUBCK signals, the external V-driver circuit usually inverts
these signals. Carefully check the timing signals that are required
at the input and output of the V-driver circuit being used, and
adjust the polarities of the AD9920A outputs accordingly.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
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