參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/112頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 17 of 112
THEORY OF OPERATION
Figure 15 shows the typical system block diagram for the AD9920A
in master mode. The CCD output is processed by the AD9920A
AFE circuitry, which consists of a CDS, black level clamp, and
ADC. The digitized pixel information is sent to the digital image
processor chip, which performs the postprocessing and com-
pression. To operate the CCD, all CCD timing parameters are
programmed into the AD9920A from the system microprocessor
through the 3-wire serial interface. From the master clock, CLI,
provided by the image processor or external crystal, the AD9920A
generates the CCD horizontal and vertical clocks and the internal
AFE clocks. External synchronization is provided by a sync pulse
from the microprocessor, which resets the internal counters and
resyncs the VD and HD outputs.
CCDIN
GPO1 TO GPO8
H1 TO H8, HL,
RG, VSUB
V1A TO V16, SUBCK
CCD
AD9920A
AFETG
V-DRIVER
DIGITAL
IMAGE
PROCESSING
ASIC
D0 TO D11
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
MICROPROCESSOR
06
87
8-
01
5
Figure 15. Typical System Block Diagram, Master Mode
Alternatively, the AD9920A can be operated in slave mode. In
this mode, the VD and HD are provided externally from the
image processor, and all AD9920A timing is synchronized with
VD and HD.
The H-drivers for H1 to H8, HL, and RG are included in the
AD9920A, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of up to 3.6 V is supported. V1A to
V16 and SUBCK vertical clocks are included as well, allowing
the AD9920A to provide all horizontal and vertical clocks
necessary to clock data out of a CCD.
The AD9920A includes programmable general-purpose outputs
(GPOs) that can trigger mechanical shutter and strobe (flash)
circuitry.
Figure 16 and Figure 17 show the maximum horizontal and
vertical counter dimensions for the AD9920A. All internal
horizontal and vertical clocking is controlled by these counters,
which specify line and pixel locations. Maximum HD length is
16,384 pixels per line, and maximum VD length is 8192 lines
per field.
MAXIMUM COUNTER DIMENSIONS
14-BIT HORIZONTAL = 16,384 PIXELS MAXIMUM
13-BIT VERTICAL = 8192 LINES MAXIMUM
06
878
-01
6
Figure 16. Vertical and Horizontal Counters
H-COUNTER BEHAVIOR IN SLAVE MODE
In the AD9920A, the internal H-counter holds at its maximum
count of 16,383 instead of rolling over. This feature allows the
AD9920A to be used in applications that contain a line length
greater than 16,384 pixels. Although no programming values
for the vertical and horizontal signals are available beyond 8191,
the H, RG, and AFE clocking continues to operate, sampling the
remaining pixels on the line.
VD
HD
MAXIMUM VD LENGTH IS 8192 LINES
CLI
MAXIMUM HD LENGTH IS 16,384 PIXELS
06
87
8-
01
7
Figure 17. Maximum VD/HD Dimensions
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