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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 45 of 112
Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions;
within each region, a different V-sequence can be selected.
Figure 57 shows how the sequence change positions (SCPs)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the
field registers. Table 19 summarizes the registers used to create
the various fields.
The SEQ registers, one for each region, select which of the
V-sequences are active in each region. The MULT_SWEEP
registers, one for each region, are used to enable sweep mode
and/or multiplier mode in any region. The SCP registers create
the line boundaries for each region. The VDLEN register specifies
the total number of lines in the field. The HDLEN registers specify
the total number of pixels per line.
The HDLASTLEN register specifies the number of pixels in the
last line of the field.
The SGMASK register is used to enable or disable each individual
VSG output. There are two bits for each VSG output to enable
separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low
enables the output. The VSGPATSEL register assigns one of
the eight SG patterns to each VSG output. The individual SG
patterns are created separately using the SG pattern registers.
The SGACTLINE1 register specifies which line in the field
contains the VSG outputs. The optional SGACTLINE2 register
allows VSG pulses to be output on a different line. Separate
masking is not available for SGACTLINE1 and SGACTLINE2,
unless separate sequences are assigned to SGACTLINE1 and
SGACTLINE2. Note that to ensure proper SUBCK operation
when using both SGACTLINE1 and SGACTLINE2, SGACTLINE2
must be programmed to occur before SGACTLINE1.
Table 19. Field Registers (CLPOB, PBLK Masking Shown in Table 11)
Register
Length (Bits)
Range
Description
SEQ
5
0 to 31 V-sequence number
Selected V-sequence for each region in the field.
MULT_SWEEP
2
0 to 3
Enable multiplier mode and/or sweep mode for each region.
0 = multiplier off, sweep off.
1 = multiplier off, sweep on.
2 = multiplier on, sweep off.
3 = multiplier on, sweep on.
SCP
13
0 to 8191 line number
Sequence change position for each region.
VDLEN
13
0 to 8191 lines
Total number of lines in each field.
HDLASTLEN
13
0 to 8191 pixels
Length in pixels of the last HD line in each field.
VSGPATSEL
24
High/low
VSGPATSEL selects which two V-pattern toggle positions are used by each
V-output. Each bit represents one V-output: Bit 0 = XV1 output, Bit 23 =
XV24 output.
0 = use TOG1 and TOG2.
1 = use TOG3 and TOG4.
SGMASK
24
High/low, each VSG
Set high to mask each individual VSG output.
Bit 0: XV1 mask.
Bit 23: XV24 mask.
SGACTLINE1
13
0 to 8191 line number
Selects the line in the field where the VSG signals are active.
SGACTLINE2
13
0 to 8191 line number
Selects a second line in the field to repeat the VSG signals. If this register is
not used, set it equal to SGACTLINE1 or to the maximum value.
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相關(guān)代理商/技術(shù)參數(shù) |
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