參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 89/112頁(yè)
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 78 of 112
Variable Gain Amplifier (VGA)
The VGA stage provides a gain range of approximately 6 dB to
42 dB, programmable with 10-bit resolution through the serial
digital interface. A gain of 6 dB is needed to match a 1 V input
signal with the ADC full-scale range of 2 V. When compared with
1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
exact VGA gain is calculated for any gain register value by
Gain (dB) = (0.0358 × Code) + 5.76 dB
where Code is the range of 0 to 1023.
VGA GAIN REGISTER CODE
V
G
A
GA
IN
(
d
B
)
42
36
30
24
18
12
6
0
127
255
383
511
639
767
895
1023
06
87
8-
1
01
Figure 101. VGA Gain Curve
Analog-to-Digital Converter (ADC)
The AD9920A uses a high performance ADC architecture
optimized for high speed and low power. Differential non-
linearity (DNL) performance is typically better than 0.5 LSB.
The ADC uses a 2 V input range. See Figure 6, Figure 7, and
Figure 8 for typical linearity and noise performance plots for
the AD9920A.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD black level. During the optical black (shielded) pixel interval
on each line, the ADC output is compared with a fixed black
level reference, which is selected by the user in the CLAMPLEVEL
register. The value can be programmed from 0 LSB to 255 LSB
in 1023 steps.
The resulting error signal is filtered to reduce noise, and the
correction value is applied to the ADC input through a DAC.
Normally, the optical black clamp loop is turned on once per
horizontal line, but this loop can be updated more slowly to suit
a particular application. If external digital clamping is used during
the postprocessing, the AD9920A optical black clamping can be
disabled using Bit 2 in AFE Register Address 0x00. When the
loop is disabled, the CLAMPLEVEL register can still be used to
provide fixed offset adjustment.
Note that if the CLPOB loop is disabled, higher VGA gain
settings reduce the dynamic range because the uncorrected
offset in the signal path is gained up.
The CLPOB pulse should be aligned with the CCD optical black
pixels. It is recommended that the CLPOB pulse duration be at
least 20 pixels wide. Shorter pulse widths can be used, but the
ability of the loop to track low frequency variations in the black
level is reduced. See the Horizontal Timing Sequence Example
section for timing examples.
Digital Data Outputs
The AD9920A digital output data is latched using the rising
edge of the DOUTPHASE register value, as shown in Figure 100.
Output data timing is shown in Figure 25 and Figure 26. It is
also possible to leave the output latches transparent so that the
data outputs are valid immediately from the ADC. Programming
Bit 1 in AFE Register Address 0x01 to 1 sets the output latches
to transparent. The data outputs can also be disabled (three-
stated) by setting Bit 0 in AFE Register Address 0x01 to 1.
The DCLK output can be used for external latching of the
data outputs. By default, the DCLK output tracks the values
of the DOUTPHASE registers. By setting the DCLKMODE
register, the DCLK output can be held at a fixed phase, and the
DOUTPHASE register values are ignored. The DCLK output
can also be inverted with respect to the data output, using the
DCLKINV register bit.
The switching of the data outputs can couple noise back into
the analog signal path. To minimize switching noise, it is
recommended that the DOUTPHASE registers be set to the
same edge as the SHP sampling location or up to 15 edges after
the SHP sampling location. Other settings can produce good
results, but experimentation is necessary. It is recommended
that the DOUTPHASE location not occur between the SHD
sampling location and 15 edges after the SHD location. For
example, if SHDLOC = 0, DOUTPHASE should be set to an
edge location of 16 or greater. If adjustable phase is not required
for the data outputs, the output latch can be left transparent
using Bit 1 in AFE Register Address 0x01.
The data output coding is normally straight binary, but the
coding can be changed to gray coding by setting Bit 2 in AFE
Register Address 0x01 to 1.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9920BBCZ 制造商:Analog Devices 功能描述:
AD9920BBCZRL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9921BBCZ 制造商:Analog Devices 功能描述:
AD9921BBCZRL 制造商:Analog Devices 功能描述:
AD9923A 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
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