- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 23 of 112
HORIZONTAL CLAMPING AND BLANKING
The horizontal clamping and blanking pulses of the AD9920A are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK in the different
regions of each field. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout to
accommodate different image transfer timing and high speed
line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 27. These two signals are programmed inde-
pendently using the registers shown in Table 11. The start polarity
for the CLPOB (or PBLK) signal is CLPOBPOL (PBLKPOL), and
the first and second toggle positions of the pulse are CLPOBTOG1
(PBLKTOG1) and CLPOBTOG2 (PBLKTOG2). Both signals
are active low and should be programmed accordingly.
A separate pattern for CLPOB and PBLK can be programmed
for each vertical sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.
Figure 57 shows how the sequence change positions divide the
readout field into regions. By assigning a different V-sequence
to each region, the CLPOB and PBLK signals can change with
each change in the vertical timing.
CLPOB and PBLK Masking Areas
Additionally, the AD9920A allows the CLPOB and PBLK signals
to be disabled in certain lines in the field without changing any
of the existing CLPOB pattern settings.
To use CLPOB (or PBLK) masking, the CLPMASKSTART
(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)
registers are programmed to specify the start and end lines in
the field where the CLPOB (PBLK) patterns are ignored. The
three sets of start and end registers allow up to three CLPOB
(PBLK) masking areas to be created.
The CLPOB and PBLK masking registers are not specific to a
certain V-sequence; they are always active for any existing field
of timing. During operation, to disable the CLPOB masking
feature, these registers must be set to the maximum value of
0x1FFF or a value greater than the programmed VD length.
Note that to disable CLPOB (or PBLK) masking during power-up,
it is recommended that CLPMASKSTART (PBLKMASKSTART)
be set to 8191 and that CLPMASKEND (PBLKMASKEND) be
set to 0. This prevents any accidental masking caused by register
update events.
Table 11. CLPOB and PBLK Pattern Registers
Register
Length
(Bits)
Range
Description
CLPOBPOL
1
High/low
Starting polarity of CLPOB for each V-sequence.
PBLKPOL
1
High/low
Starting polarity of PBLK for each V-sequence.
CLPOBTOG1
13
0 to 8191 pixel location
First CLPOB toggle position within line for each V-sequence.
CLPOBTOG2
13
0 to 8191 pixel location
Second CLPOB toggle position within line for each V-sequence.
PBLKTOG1
13
0 to 8191 pixel location
First PBLK toggle position within line for each V-sequence.
PBLKTOG2
13
0 to 8191 pixel location
Second PBLK toggle position within line for each V-sequence.
CLPMASKSTART
13
0 to 8191 line location
CLPOB masking area—starting line within field (maximum of three areas).
CLPMASKEND
13
0 to 8191 line location
CLPOB masking area—ending line within field (maximum of three areas).
PBLKMASKSTART
13
0 to 8191 line location
PBLK masking area—starting line within field (maximum of three areas).
PBLKMASKEND
13
0 to 8191 line location
PBLK masking area—ending line within field (maximum of three areas).
相關PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復。