參數(shù)資料
型號： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 49/112頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 41 of 112
Vertical Masking Using the FREEZE/RESUME Registers
As shown in Figure 51 and Figure 52, the FREEZE/RESUME
registers are used to temporarily mask the V-outputs. The pixel
locations to begin the masking (FREEZE) and end the masking
(RESUME) create an area in which the vertical toggle positions
are ignored. At the pixel location specified in the FREEZE register,
the V-outputs are held static at their current dc state, high or low.
The V-outputs are held until the pixel location specified by the
RESUME register is reached, at which point the signals continue
with any remaining toggle positions, if any exist.
Four sets of FREEZE/RESUME registers are provided, allowing
the vertical outputs to be interrupted up to four times in the
same line.
When masking is enabled, each group (Group A, Group B,
Group C, and Group D) uses the same FREEZE/RESUME
positions.
Note that the FREEZE/RESUME registers are also used as the
VALTSEL0 and VALTSEL1 registers during special vertical
alternation mode (see the Special Vertical Sequence Alternation
(SVSA) Mode section).
XV1
XV24
HD
NO MASKING AREA
06
87
8-
0
50
Figure 51. No FREEZE/RESUME
XV1
XV24
HD
V-MASKING AREA
FREEZE
RESUME
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. FOUR SEPARATE MASKING AREAS ARE AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, AND
FREEZE4/RESUME4 REGISTERS.
06
87
8-
05
1
Figure 52. Using FREEZE/RESUME
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