- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 90/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 79 of 112
APPLICATIONS INFORMATION
POWER-UP SEQUENCE FOR MASTER MODE
When the AD9920A is powered up, the following sequence is
recommended (refer to Figure 102 for each step). Note that a
SYNC signal is required for master mode operation. If an external
SYNC pulse is not available, it is possible to generate an internal
SYNC event by writing to the SWSYNC register.
1.
Turn on the 3 V and 1.8 V power supplies for the
AD9920A and start master clock CLI.
2.
The SYNC/RST pin is configured as the RST pin by
default. It must be brought high before any register writes
are performed. Configure the SYNC/RST pin for SYNC
functionality by writing Register 0x12 = 0x00, and then
perform a software reset by writing Register 0x10 to 0x01.
3.
Make sure that VDR_EN is low. If driving VDR_EN with a
GPO, set the appropriate bit in the GPO_OUTPUT_EN
register (Address 0x7A, Bits[23:16]) to 1 to configure it as
an output and make sure that the appropriate bit in the
GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0.
4.
Power up the V-driver supplies.
5.
Define the standby status of the AD9920A vertical outputs.
Write to the Standby2 and Standby3 polarity registers
(Address 0x25 and Address 0x26 = 0x1FF8000).
Write 0xFF8000 to Address 0x1C to configure the XV and
VSG signals. Write 0x100000 to Register 0xD1. When using
3-phase HCLK mode, enable this mode before Step 6 by
setting Address 0x24 = 0x10.
6.
Place the AFE into normal operation and enable clamping
(Address 0x00 = 0x04). If using CLO to drive a crystal, set
OSC_RST = 1. Wait at least 500 μs before performing Step 8.
7.
Load the required registers to configure vertical timing,
horizontal timing, high speed timing, and shutter timing.
8.
Reset the internal timing core (TGCORE_RST). If a 2× clock
is used for CLI, the CLIDIVIDE register (Address 0x0D)
should be set to 1 before TGCORE_RST is written
(Address 0x14 = 0x01). Wait at least 100 μs before
performing Step 9.
9.
Bring the VDR_EN pin high. If driving VDR_EN with
a GPO, write to the appropriate GPO polarity bit in
Address 0x7A to set the VDR_EN signal high (updated at
the next VD). Note that IOVDD must be at the same
voltage as VDVDD if GPO is used for VDR_EN.
10. Enable the AD9920A outputs (OUT_CONTROL register,
Address 0x11 = 0x01). OUT_CONTROL is a VD-updated
register; therefore, the outputs become active after the next
VD falling edge.
11. Enable master mode operation by setting Register 0x20 =
0x01.
12. Generate a SYNC event. SYNC should be high at power-
up. Bring the SYNC input low for a minimum of 100 ns,
and then bring SYNC high again. This resets the internal
counters and starts VD/HD operation. The first VD/HD
edge allows VD-updated register updates (including updates
of OUT_CONTROL) to occur, enabling all outputs. If a
hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit 24) can be used to initiate a SYNC event.
Note that VDR_EN must remain high to achieve proper vertical
outputs during normal operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。