參數(shù)資料
型號: AD9920ABBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 36/112頁
文件大?。?/td> 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
標準包裝: 2,000
位數(shù): 12
電壓 - 電源,模擬: 1.6 V ~ 2 V
電壓 - 電源,數(shù)字: 1.6 V ~ 2 V
封裝/外殼: 105-LFBGA,CSPBGA
供應商設備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9920A
Rev. B | Page 3 of 112
REVISION HISTORY
6/10—Rev. A to Rev. B
Changes to Figure 1...........................................................................1
Changes to Figure 9, Figure 10, Figure 12, and Figure 13 .........15
Moved Terminology Section..........................................................16
Changes to Figure 15 ......................................................................17
Moved Generating HBLK Line Alternation Section ..................24
Moved Figure 32..............................................................................25
Moved Figure 33..............................................................................27
Changes to Vertical Sequences (VSEQ) Section .........................34
Changes to Special Vertical Sequence Alternation
(SVSA) Mode Section .....................................................................38
Added Table 18; Renumbered Tables Sequentially.....................44
Deleted Figure 77; Renumbered Figures Sequentially ...............61
Changes to SUBCK Low Speed Operation Section
and Table 43 .....................................................................................61
Changes to Figure 81 ......................................................................62
Changes to Table 45 ........................................................................64
Changes to Scheduled Toggles Section and Figure 85 ...............66
Changes to Figure 86, ShotTimer Sequences Section,
and Figure 87 ...................................................................................67
Changes to Complete Exposure/Readout Operation
Using Primary Counter and GPO Signals Section .....................69
Changes to Triggered Control of GPO5 Section.........................71
Changes to Figure 96 ......................................................................75
Changes to Figure 100 ....................................................................77
Changes to Figure 102 ....................................................................80
Changes to Power-Up Sequence for Slave Mode Section ..........81
Changes to Figure 103 ....................................................................82
Changes to Power-Down Sequence for Master and
Slave Modes Section........................................................................83
Added Table 48; Renumbered Tables Sequentially.....................86
Changes to Figure 108 ....................................................................88
Changes to Figure 109 ....................................................................89
Changes to Figure 110 ....................................................................90
Changes to Figure 111 ....................................................................91
Changes to Figure 112 ....................................................................92
Changes to Layout of Internal Registers Section
and Figure 115 .................................................................................94
Changes to Table 53 ........................................................................97
Changes to Table 57 ........................................................................99
Changes to Table 59 ......................................................................101
Changes to Table 61 ......................................................................105
Changes to Table 63 ......................................................................108
Updated Outline Dimensions......................................................112
6/09—Revision A: Initial Version
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