CL = 20 pF, AVDD = DVDD = TCVDD = " />
參數(shù)資料
型號： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 80/112頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 7 of 112
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, fCLI = 40.5 MHz, unless otherwise noted.
Table 4.
Parameter
Test Conditions/
Comments
Symbol
Min
Typ
Max
Unit
MASTER CLOCK
CLI Clock Period
tCONV
24.7
ns
CLI High/Low Pulse Width
0.8 × tCONV/2
tCONV/2
1.2 × tCONV/2
ns
Delay from CLI Rising Edge to Internal
Pixel Position 0
tCLIDLY
6
ns
SLAVE MODE SPECIFICATIONS
VD Falling Edge to HD Falling Edge
tVDHD
0
VD period tCONV
ns
HD Falling Edge to CLI Rising Edge
Only valid if OSC_RST = 0
tHDCLI
3
tCONV 2
ns
HD Falling Edge to CLO Rising Edge
Only valid if OSC_RST = 1
tHDCLO
3
tCONV 2
ns
CLI Rising Edge to SHPLOC
Internal sample edge
tCLISHP
3
tCONV 2
ns
AFE
SHPLOC Sample Edge to SHDLOC
Sample Edge
tS1
0.8 × tCONV/2
tCONV/2
tCONV tS2
ns
SHDLOC Sample Edge to SHPLOC
Sample Edge
tS2
0.8 × tCONV/2
tCONV/2
tCONV tS1
ns
AFE Pipeline Delay
16
Cycles
AFE CLPOB Pulse Width
2
20
Pixels
DATA OUTPUTS
Output Delay from DCLK Rising Edge
tOD
1
ns
Pipeline Delay from SHP/SHD
Sampling to Data Output
16
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
Must not exceed CLI
frequency
fSCLK
40.5
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
TIMING CORE SETTING RESTRICTIONS
Inhibited Region for SHP Edge
Location1
tSHPINH
50
62
Edge
location
Inhibited Region for SHP or SHD with
Respect to H-Clocks2, 3, 4
See Figure 23 and
RETIME = 0, MASK = 0
tSHDINH
HxNEGLOC 14
HxNEGLOC 2
Edge
location
RETIME = 0, MASK = 1
tSHDINH
HxPOSLOC 14
HxPOSLOC 2
Edge
location
RETIME = 1, MASK = 0
tSHPINH
HxNEGLOC 14
HxNEGLOC 2
Edge
location
RETIME = 1, MASK = 1
tSHPINH
HxPOSLOC 14
HxPOSLOC 2
Edge
location
Inhibited Region for DOUTPHASE Edge
Location
tDOUTINH
SHDLOC + 1
SHDLOC + 12
Edge
location
1 Applies only to slave mode operation. The inhibited area for SHP is needed to meet the timing requirement for tCLISHP for proper H-counter reset operation.
2 When the HBLKRETIME bits (Address 0x35, Bits[3:0]) are enabled, the inhibit region for the SHD location changes to the inhibit region for the SHP location.
3 When the HBLK masking polarity registers (V-sequence Register 0x18[24:21]) are set to 0, the H-edge reference becomes HxNEGLOC.
4 The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1; Mode 2 = H1, H2; Mode 3 = H1, H3; and 3-Phase Mode = Phase 1,
Phase 2, and Phase 3.
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