- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 70/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁當前第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 60 of 112
XSUBCNT
SUBCK
XSUBCK
VH
VMM
VLL
06
87
8-
0
80
Figure 80. XSUBCNT, XSUBCK, and SUBCK Output Polarities
V-DRIVER SLEW RATE CONTROL
SUBSTRATE CLOCK OPERATION (SUBCK)
The AD9920A allows the user to moderate the slew rates of the
V-driver outputs when transitioning to VM and VL (this feature
does not affect transitions to VH). This feature minimizes cou-
pling from V-driver activity that occurs while the AD9920A is
clocking valid image pixel data out of the CCD.
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9920A supports three types of
electronic shuttering: normal, high precision, and low speed.
Along with the SUBCK pulse placement, the AD9920A can
accommodate different readout configurations to further
suppress the SUBCK pulses during multiple field readouts.
There are both coarse and fine mechanisms for controlling the
slew rate of the V1A to V13 outputs. If SRSW = VDD and
SRCTL = VDD, the V1A to V13 switches have roughly 10%
of their normal drive strength (that is, when SRSW = VSS).
If SRSW = VDD and SRCTL < VDD, the voltage applied to
SRCTL controls the slew rate for V1A to V13 transitions from
VM to VL and from VL to VM. For values from 800 mV to
VDD, V1A to V13 transition at a fraction of their maximum
slew rate that is roughly proportional to the voltage applied to
SRCTL. (It is not recommended that voltages less than 800 mV
be applied to SRCTL.)
The SUBCK signal is a programmable string of pulses, each
occupying a line following the primary sense gate active line,
SGACTLINE1 (see Table 43). The SUBCK signal has program-
mable pulse width, line placement, and number of pulses to
accurately control the exposure time.
SUBCK Normal Operation
By default, the AD9920A operates in the normal SUBCK
configuration, in which the SUBCK signal is pulsing in every
VD field (see Figure 81). The SUBCK pulse occurs once per
line, and the total number of repetitions within the field
determines the length of the exposure time. The SUBCK
pulse polarity and toggle positions within a line are program-
mable using the SUBCK_POL and SUBCK_TOG1 registers
(see Table 43). The number of SUBCK pulses per field is
programmed in the SUBCKNUM register (Address 0x75).
The user must tune this voltage for the specific system to
determine the optimal setting that ensures maximum charge
transfer efficiency and minimizes any coupling from V-driver
activity into the image. V14, V15, and V16 are permanently
weak compared with V1A to V13 and are not affected by the
slew rate control function. Note that the slew rate control
feature is intended only for use with CCDs that require V-driver
activity outside the normal horizontal clock blanking region.
As shown in Figure 81, the SUBCK pulses always begin in the line
following the SG active line, which is specified in the SGACTLINE
registers for each field. The SUBCK_POL, SUBCK_TOG1,
SUBCK_TOG2, SUBCKNUM, and SUBCKSUPPRESS registers
are updated at the start of the line after the sensor gate line, as
described in the Updating New Register Values section.
SHUTTER TIMING CONTROL
The AD9920A supports the generation of electronic shuttering
(SUBCK) and also features flexible general-purpose outputs
(GPOs) to control mechanical shuttering, CCD substrate bias
switching, and strobe circuitry. In the following sections, the
terms sense gate (SG) and vertical sense gate (VSG) are used
interchangeably.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復。