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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/112頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 18 of 112
HIGH SPEED PRECISION TIMING CORE
The AD9920A generates high speed timing signals using the
flexible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE; it
includes the reset gate (RG), horizontal drivers (H1 to H8, HL),
and SHP/SHD sample clocks. A unique architecture makes it
routine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout
and the AFE correlated double sampling.
The high speed timing of the AD9920A operates the same
way in either master or slave mode configuration. For more
information on synchronization and pipeline delays, see
the Power-Up Sequence for Master Mode section.
Timing Resolution
The Precision Timing core uses a 1× master clock input as a
reference (CLI). This clock should be the same as the CCD pixel
clock frequency. Figure 18 illustrates how the internal timing core
divides the master clock period into 64 steps or edge positions.
Using a 40.5 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 0.4 ns. If a 1× system clock
is not available, it is possible to use a 2× reference clock by pro-
gramming the CLIDIVIDE register (AFE Register Address 0x0D).
The AD9920A then internally divides the CLI frequency by 2.
High Speed Clock Programmability
Figure 19 shows when the high speed clocks RG, H1 to H8, HL,
SHP, and SHD are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. Horizontal Clock H1 has programmable rising and falling
edges and polarity control. In HCLK Mode 1, H3, H5, and H7
are equal to H1. H2, H4, H6, and H8 are always inverses of H1.
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 23 shows the default
timing locations for all of the high speed clock signals.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
P[0]
P[64] = P[0]
P[16]
P[32]
P[48]
1 PIXEL
PERIOD
...
CLI
tCLIDLY
POSITION
tCLIDLY = 6 ns TYP).
06
87
8-
01
8
tCONV
Figure 18. High Speed Clock Resolution from CLI, Master Clock Input
HL
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1SHP SAMPLE LOCATION.
2SHD SAMPLE LOCATION.
3RG RISING EDGE.
4RG FALLING EDGE.
5H1 RISING EDGE.
6H1 FALLING EDGE.
7HL RISING EDGE.
8HL FALLING EDGE.
1
2
34
78
H2, H4, H6, H8
H1, H3, H5, H7
56
0
68
78
-01
9
Figure 19. High Speed Clock Programmable Locations (HCLKMODE = 0x01)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
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| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
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