參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/112頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 32 of 112
VERTICAL TIMING GENERATION
The AD9920A provides a flexible solution for generating vertical
CCD timing and can support multiple CCDs and different system
architectures. The vertical transfer clocks are used to shift each
line of pixels into the horizontal output register of the CCD. The
AD9920A allows these outputs to be individually programmed
into various readout configurations by using a four-step process.
1.
The individual pulse patterns for XV1 to XV24 are created
by using the vertical pattern group registers.
2.
The V-pattern groups are used to build the V-sequences
where additional information is added.
3.
The readout for an entire field is constructed by dividing
the field into regions and then assigning a sequence to each
region. Each field can contain up to nine different regions
to accommodate the various steps of the readout, such as
high speed line shifts and unique vertical line transfers.
The total number of V-patterns, V-sequences, and fields is
programmable but limited by the number of registers.
4.
The mode registers allow the different fields to be combined
in any order for various readout configurations.
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
XV1
XV2
XV23
XV24
XV1
XV2
XV3
FIELD1
FIELD2
FIELD3
REGION 2: USE V-SEQUENCE 3
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD1
FIELD4
FIELD2
XV3
XV23
XV24
VPAT0
XV1
XV2
XV23
XV24
XV3
XV1
XV2
XV23
XV24
XV3
XV1
XV2
XV23
XV24
XV3
VPAT1
1
2
3
4
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
V-SEQUENCE 0
(VPAT0, 1 REP)
V-SEQUENCE 1
(VPAT1, 2 REP)
V-SEQUENCE 2
(VPAT1, N REP)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
ARE USED AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS CAN BE COMBINED IN ANY ORDER).
06
87
8-
0
40
Figure 41. Summary of Vertical Timing Generation
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9920BBCZ 制造商:Analog Devices 功能描述:
AD9920BBCZRL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9921BBCZ 制造商:Analog Devices 功能描述:
AD9921BBCZRL 制造商:Analog Devices 功能描述:
AD9923A 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
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