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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 108/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 95 of 112
UPDATING NEW REGISTER VALUES
The AD9920A internal registers are updated at different times,
depending on the particular register. Table 51 summarizes the
four register update types: SCK, VD, SG line, and SCP. Tables in
the Complete Register Listing section contain an update type
column that identifies when each register is updated.
Table 51. Register Update Locations
Update Type
Description
SCK
When the 28th data bit (D27) is clocked in, the
register is immediately updated.
VD
Register is updated at the next VD falling edge.
VD-updated registers can be delayed further by
using the update register at Address 0x17. Field
registers are not affected by the update register.
SG Line
Register is updated at the HD falling edge at the
start of the SG active line.
SCP
Register is updated at the next SCP when the
register is used.
SCK-Updated Registers
As soon as the 28th data bit (D27) is clocked in, some registers
are immediately updated. These registers are used for functions
that do not require gating with the next VD boundary, such as
power-up and reset functions.
VD-Updated Registers
More registers are updated at the next VD falling edge. By
updating these values at the next VD edge, the current field is
not corrupted, and the new register values are applied to the
next field. The VD update can be further delayed past the VD
falling edge by using the update register (Address 0x17). This
delays the VD-updated register updates to any HD line in the
field. Note that the field registers are not affected by the update
register.
SG Line-Updated Registers
A few of the shutter registers are updated at the HD falling edge
at the start of the SG active line. These registers control the
SUBCK signal so that the SUBCK output is not updated until
the SG line occurs.
SCP-Updated Registers
At the next SCP where they are used, the V-pattern group and
V-sequence registers are updated. For example, in Figure 117
this field has selected Region 1 to use VSEQ3 for the vertical
outputs. This means that a write to any of the VSEQ3 registers
or to any of the V-pattern group registers that are referenced by
VSEQ3, updates at SCP1. If multiple writes are done to the same
register, the last one done before SCP1 is the one that is updated.
Likewise, register writes to any VSEQ5 registers are updated at
SCP2, and register writes to any VSEQ8 registers are updated
at SCP3.
Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge where
a sequence change position (SCP) occurs. See Figure 107 for an
example of what this inhibit area looks like in master and slave
modes. This restriction applies to the V-pattern, V-sequence,
and field registers. As shown in Figure 117, writing to these
registers before the VD falling edge typically avoids loading
these registers during SCP locations.
VD
REGION 0
HD
SCP1
SCP2
SCP3
REGION 1
REGION 2
REGION 3
VSG
SGLINE
SCP0
SERIAL
WRITE
SCK
UPDATED
SCP0
VD
UPDATED
SG
UPDATED
SCP
UPDATED
XV1 TO XV24
USE VSEQ2
USE VSEQ3
USE VSEQ5
USE VSEQ8
06
87
8-
1
17
Figure 117. Register Update Locations (See Table 51 for Definitions)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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