參數(shù)資料
型號： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 93/112頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 81 of 112
POWER-UP SEQUENCE FOR SLAVE MODE
When the AD9920A is used in slave mode, the VD/HD inputs
are used to synchronize the internal counters. For more detail
on the counter reset operation, see Figure 103.
1.
Turn on the 3 V and 1.8 V power supplies for the
AD9920A, and start master clock CLI.
2.
Reset the internal AD9920A registers.
If the SYNC/RST pin is functioning as RST, apply a rising
edge to the SYNC/RST pin. If the SYNC/RST pin is function-
ing as SYNC, tie this pin high. Then perform a software
reset by writing Register 0x10 to 0x01.
3.
Make sure that VDR_EN is low. If driving VDR_EN with a
GPO, set the appropriate bit in the GPO_OUTPUT_EN
register (Address 0x7A, Bits[23:16]) to 1 to configure it as
an output and make sure that the appropriate bit in the
GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0.
4.
Power up the V-driver supplies.
5.
Define the standby status of the AD9920A vertical outputs.
Write to the Standby2 and Standby3 polarity registers
(Address 0x25 and Address 0x26 = 0x1FF8000).
Write 0xFF8000 to Address 0x1C to configure the XV
and VSG signals. Write 0x100000 to Register 0xD1. When
using 3-phase HCLK mode, enable this mode before Step 6
by setting Address 0x24 = 0x10.
6.
Place the AFE into normal operation and enable clamping
(Address 0x00 = 0x04). If using CLO to drive a crystal, set
OSC_RST = 1. Wait at least 500 μs before performing Step 8.
7.
Load the required registers to configure vertical timing,
horizontal timing, high speed timing, and shutter timing.
8.
Reset the internal timing core (TGCORE_RST).
If a 2× clock is used for CLI, the CLIDIVIDE register
(Address 0x0D) should be set to 1 before TGCORE_RST is
written (Address 0x14 = 0x01). Wait at least 100 μs before
performing Step 9.
9.
Bring the VDR_EN pin high. If driving VDR_EN with
a GPO, write to the appropriate GPO polarity bit
(Address 0x7A) to set the VDR_EN signal high (updated at
the next VD). Note that IOVDD must be at the same
voltage as VDVDD if GPO is used for VDR_EN.
10. Enable the AD9920A outputs (OUT_CONTROL register,
Address 0x11 = 0x01). OUT_CONTROL is a VD-updated
register; therefore, the outputs become active after the next
VD falling edge.
11. Enable slave mode operation by setting Register 0x0E = 0x100.
12. Start VD and HD timing to synchronize the internal
counters and begin operation. VD-updated registers are
updated at the first VD falling edge.
Note that VDR_EN must remain high to achieve proper vertical
outputs during normal operation.
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