- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 26 of 112
Table 12. HBLK Pattern Registers
Register
Length
(Bits)
Range
Description
HBLK_MODE
2
0 to 1 HBLK modes
Enables different HBLK toggle position operations.
0 = normal mode; six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even and odd lines to the
same value. In addition to the six toggle positions, the HBLKSTART, HBLKEND,
HBLKLEN, and HBLKREP registers can be used to generate HBLK patterns. If even/
odd alternation is not needed, set toggles for even and odd lines to the same value.
1 = advanced HBLK mode; divides HBLK interval into six repeat areas.
Uses HBLKSTARTA/B/C and RAxHxREPA/B/C registers; the latter, depending on the
mode of operation, are stored in the HBLKTOGO1 to HBLKTOGO6 and HBLKTOGE1
to HBLKTOGE6 registers (Address 0x19 to Address 0x1E; see Table 63).
2 = test mode only; do not access.
3 = test mode only; do not access.
HBLKSTART
13
0 to 8191 pixel location
Start location for HBLK in HBLK Mode 0 and HBLK Mode 1.
HBLKEND
13
0 to 8191 pixel location
End location for HBLK in HBLK Mode 0 and HBLK Mode 1.
HBLKLEN
13
0 to 8191 pixels
HBLK length in HBLK Mode 0 and HBLK Mode 1.
HBLKREP
13
0 to 8191 repetitions
Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1.
HBLKMASK_H1
1
High/low
Masking polarity for H1/H3/H5/H7 during HBLK.
HBLKMASK_H2
1
High/low
Masking polarity for H2/H4/H6/H8 during HBLK.
HBLKMASK_HL
1
High/low
Masking polarity for HL during HBLK.
HBLKMASK_H3P
1
High/low
Masking polarity for H3P during 3-phase mode during HBLK.
HBLKTOGO1
13
0 to 8191 pixel location
First HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO2
13
0 to 8191 pixel location
Second HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO3
13
0 to 8191 pixel location
Third HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO4
13
0 to 8191 pixel location
Fourth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO5
13
0 to 8191 pixel location
Fifth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO6
13
0 to 8191 pixel location
Sixth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGE1
13
0 to 8191 pixel location
First HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE2
13
0 to 8191 pixel location
Second HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE3
13
0 to 8191 pixel location
Third HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE4
13
0 to 8191 pixel location
Fourth HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE5
13
0 to 8191 pixel location
Fifth HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE6
13
0 to 8191 pixel location
Sixth HBLK toggle position for even lines in HBLK Mode 0.
RA0H1REPA/B/C
12
0 to 15 HCLK pulses for
each A, B, and C
HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in
HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT.
Bits[3:0]: RA0H1REPA. Number of H1 pulses following HBLKSTARTA.
Bits[7:4]: RA0H1REPB. Number of H1 pulses following HBLKSTARTB.
Bits[11:8]: RA0H1REPC. Number of H1 pulses following HBLKSTARTC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。