tDOUTINH tSHPINH<" />
參數(shù)資料
型號: AD9920ABBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 27/112頁
文件大?。?/td> 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
電壓 - 電源,模擬: 1.6 V ~ 2 V
電壓 - 電源,數(shù)字: 1.6 V ~ 2 V
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9920A
Rev. B | Page 21 of 112
06
87
8-
0
23
tDOUTINH
tSHPINH
tSHDINH
P[0]
CLI
RG
P[64] = P[0]
CCD
SIGNAL
P[32]
P[16]
P[48]
POSITION
H2
RGr[0]
RGf[16]
SHD
SHDLOC[0]
H1
H1r[0]
H1f[32]
tS1
SHP
SHPLOC[32]
DOUTPHASEP
50
62
1
12
tS2
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
4. THE tSHPINH AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.
5. THE tSHDINH AREA WILL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE
H1HBLK MASKING POLARITY.
6. THE tSHDINH AREA CAN ALSO BE CHANGED TO A tSHPINH AREA IF THE H1HBLKRETIME BIT = 1.
Figure 23. High Speed Timing Default Locations
P[0]
RG
P[64] = P[0]
CCD
SIGNAL
P[32]
P[16]
P[48]
TAP POSITION
PHASE 1
RGr[0]
RGf[16]
SHD
SHDLOC[0]
HL
HLr[0]
HLf[32]
tS1
SHP
SHPLOC[32]
PHASE 2
PHASE 3
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN USING 3-PHASE HBLK MODE.
2. THE RISING EDGE OF EACH HCLK PHASE HAS AN ASSOCIATED SHDINH.
3. WHEN THE HBLK RETIME BITS (0x35 [3:0]) ARE ENABLED, THE INHIBITED AREA BECOMES SHPINH.
4. WHEN THE HBLK MASK LEVEL FOR PHASE 1, 2, OR 3 IS CHANGED TO LOW, THE INHIBIT AREA IS
REFERENCED TO THE HCLK FALLING EDGE, INSTEAD OF THE HCLK RISING EDGE.
06
87
8-
0
24
SHDINH/SHPINH
Figure 24. High Speed Timing Typical Locations, 3-Phase HCLK Mode
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