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參數(shù)資料
| 型號： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁數(shù)： | 82/130頁 |
| 文件大?。?/td> | 650K |
| 代理商： | ZPSD813F1V |
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PSD813F Famly
Prelimnary
78
9.6.1 Standard JTAGSignals (cont.)
The PSD813F supports JTAG In-System-Configuration (ISC) commands, but not Boundary
Scan. A definition of these JTAG-ISC commands and sequences are defined in a
supplemental document available from WSI. WSI’s PSDsoft software tool and FlashLink
JTAG programming cable implement these JTAG-ISC commands. This document is needed
only as a reference for designers who use a FlashLink to program their PSD813F.
9.6.2 JTAGExtensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE”
command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are
used to speed programming and erase functions by indicating status on PSD pins instead
of having to scan the status out serially using the standard JTAG channel. See Application
Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until an “ISC_CLEAR” command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command. TERR does not apply to EEPROM.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be
high when the PSD813F device is in read array mode (Flash memory and EEPROM
contents can be read). TSTAT will be low when Flash memory programming or erase cycles
are in progress, and also when data is being written to EEPROM.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection of TSTAT signals from several PSD813F
devices and a wired-OR connection of TERR signals from those same devices. This is
useful when several PSD813F devices are “chained” together in a JTAG environment.
9.6.3 Security and Flash Memories and EEPROM Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft Configuration.
All Flash Memory and EEPROM sectors can individually be sector protected against
erasures. The sector protect bits can be set in PSDsoft Configuration.
The
PSD813F
Functional
Blocks
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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