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參數資料
| 型號： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁數： | 34/130頁 |
| 文件大?。?/td> | 650K |
| 代理商： | ZPSD813F1V |
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PSD813F Famly
Prelimnary
30
The
PSD813F
Functional
Blocks
(cont.)
9.1.2 SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The SRAM is enabled when RS0—the SRAM
chip select output from the DPLD—is high. RS0 can contain up to two product terms,
allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PC2). If you have an external battery connected to the
PSD813F, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover to
the battery occurs.
Pin PC4 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the
battery voltage and the battery on PC2 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft Configuration.
9.1.3 Memory Select Signals
The main Flash (FSi), optional EEPROM or Flash Boot (EESi/CSBOOTi), and SRAM (RS0)
memory select signals are all outputs of the DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the equations for the internal chip select
signals:
1. Flash memory and EEPROM or Flash Boot memory sector select signals must
not
be
larger than the physical sector size.
2. Any main Flash memory sector must
not
be mapped in the same memory space as
another Flash sector.
3. An EEPROM/Flash Boot memory sector must
not
be mapped in the same memory
space as another EEPROM/Flash Boot sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5. An EEPROM/Flash Boot memory sector
may
overlap a main Flash memory sector.
In case of overlap, priority will be given to the EEPROM/Flash Boot sector.
6. SRAM, I/O, and Peripheral I/O spaces
may
overlap any other memory sector. Priority
will be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, EES0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of EES0 greater than 87FFh (and
less than 9FFFh) will automatically address EEPROM memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EEPROM segment 0 can not be accessed in
this example. Also note that an equation that defined FS1 to anywhere in the range of
8000h to BFFFh would
not
be valid.
Figure 7 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must
not
overlap. Level one has the highest priority and level 3 has the lowest.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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