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參數(shù)資料
| 型號(hào)： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 19/130頁(yè) |
| 文件大?。?/td> | 650K |
| 代理商： | ZPSD813F1V |
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Prelimnary
PSD813F Famly
15
9.0
The
PSD813F
Functional
Blocks
As shown in Figure 1, the PSD813F consists of six major types of functional blocks:
J
Memory Blocks
J
PLDBlocks
J
Bus Interface
J
I/OPorts
J
Power Management Unit
J
JTAGInterface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD813F has the following memory blocks:
The main Flash memory
Optional secondary EEPROM or Flash boot memory
Optional SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes which versions of the PSD813F contain which memory blocks.
Device
Main Flash
128KB
EEPROM
32KB
Flash Boot Memory
32K
SRAM
2KB
PSD813F1
PSD813F2
PSD813F3
PSD813F4
PSD813F5
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
No
Yes
No
Yes
Yes
Yes
No
No
Table 8. Memory Blocks
9.1.1 Main Flash and Optional Secondary EEPROM or Flash Boot Memory Description
The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The
optional EEPROM or Flash Boot memory is divided into four sectors of eight Kbytes
each. Each sector of either memory can be separately protected from program and erase
operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
EEPROM may be programmed byte-by-byte or sector-by-sector, and erasing is automatic
and transparent. The integrity of the data can be secured with the help of Software Data
Protection (SDP). Any write operation to the EEPROM is inhibited during the first five
milliseconds following power-up.
During a program or erase of Flash, or during a write of the EEPROM, the status can be
output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft Configuration.
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