參數(shù)資料
型號： ZPSD813F1V
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 6/130頁
文件大?。?/td> 650K
代理商： ZPSD813F1V
PSD813F Famly
Prelimnary
2
1.0
Introduction
(Cont.)
Please refer to the revision block at the end of this
document for updated information.
The PSD813F family includes a JTAG serial programming interface to allow in-system-
programming of the
entire device
. This feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the cost of field upgrades. Using WSI’s special
Fast-JTAG programming, a design can be programmed into the PSD813F in as little as
seven seconds.
The innovative Flash PSD813F family solves key problems faced by designers when
managing discrete Flash memory devices, such as:
First-time programming
Complex address decoding
Simultaneous read and write to Flash.
The PSD813F’s serial JTAG interface allows in-system-programming and eliminates the
need for a boot EPROM or an external programmer. To simplify Flash updates, the
PSD813F1, PSD813F2, and PSD813F4 devices perform program execution out of a
secondary EEPROM (F1) or Flash (F2/F4) memory block while the main Flash memory is
being updated. This solution avoids the complicated overhead circuitry and software
necessary to implement in-system Flash memory updates.
PSDsoft —WSI’s software development tool—now has the ability to generate ANSI-C
compliant code for use with your target MCU. The code generated allows you to manipulate
the non-volatile memory (NVM) within the PSD. Code examples are also provided for:
Flash ISP via the UART of the host MCU
Memory paging to execute code across several PSD memory pages
Loading, reading, and manipulation of PSD Micro
Cells by the MCU
The PSD813F is available in a 52-pin PLCC package and a 64-pin plastic Thin Quad
Flatpack (TQFP) package.
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80186, 80C251, and 80386EX
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80 and Z8
NEURON
3150 CHIP
TM
.
J
Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
J
Optional internal secondary 256 Kbit EEPROM or Flash boot memory. It is divided into
four equal-sized blocks that can be accessed with user-specified addresses. This
secondary memory brings the ability to execute code and update the main Flash
concurrently.
J
Optional 16 Kbit scratchpad SRAM. The SRAM’s contents can be protected from a
power failure by connecting an external battery.
2.0
Key Features
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相關代理商/技術參數(shù)
參數(shù)描述
ZPSD813F1V-15J 制造商:WSI 功能描述:
ZPSD813F1V-15J-CC790 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals
ZPSD813F1V-20J 制造商:WSI 功能描述:
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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