
PSD813F Family
Preliminary
76
Port C Pin
PC0
JTAG Signals
TMS
Description
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
Table 34. JTAG Port Signals
The
PSD813F
Functional
Blocks
(cont.)
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD813F can be enabled on Port C (see Table 34). All memory
(Flash and EEPROM), PLD logic, and PSD configuration bits may be programmed through
the JTAG interface. A blank part can be mounted on a printed circuit board and
programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See WSI Application Note 54 for more details on JTAG In-System-Programming.
*
SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
Port Configuration
MCU I/O
PLD Output
Power On Reset
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Tri-stated
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Tri-stated
Address Out
Data Port
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Register
PMMR0, 2
Micro
Cells Flip
Flop status
Power On Reset
Cleared to “0”
Cleared to “0” by
internal power on
reset
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
Warm Reset
Unchanged
Depend on .re and
.pr equations
Power Down Mode
Unchanged
Depend on .re and
.pr equations
VM Register*
Initialized based on
the selection in
PSDsoft
Configuration Menu
Cleared to “0”
Unchanged
All other registers
Unchanged