- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382773 > ZPSD813F1V Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM) PDF資料下載
參數(shù)資料
| 型號： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁數(shù)： | 78/130頁 |
| 文件大?。?/td> | 650K |
| 代理商： | ZPSD813F1V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
PSD813F Famly
Prelimnary
74
APD
ALE
Enable Bit
0
1
1
1
PD Polarity
X
X
1
0
ALE Level
X
Pulsing
1
0
APDCounter
Not Counting
Not Counting
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
Table 32. APDCounter Operation
The
PSD813F
Functional
Blocks
(cont.)
9.5.2 Oher Power Saving Options
The PSD813F offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are enabled
by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD(ZPSD813F)
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By
setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased by 10 ns after the Turbo bit is set to “1” (turned off) when the
inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a
“0” (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay.
Note:
Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD813F supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PC2) that can be connected to an
external battery. When V
CC
becomes lower than Vstby then the PSD will automatically
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 μA. The SRAM data retention voltage is 2 V minimum. The battery-on indicator
(Vbaton) can be routed to PC4. This signal indicates when the V
CC
has dropped below the
Vstby voltage.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, EEPROM, SRAM, and I/O for read or write
operations involving the PSD813F. A high on the CSI pin will disable the Flash memory,
EEPROM, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O
pins remain operational when CSI is high.
Note:
there may be a timing penalty when using
the CSI pin depending on the speed grade of the PSD that you are using. See the timing
parameter t
SLQV
in the AC/DC specs.
9.5.2.4 Input Clock
The PSD813F provides the option to turn off the CLKIN input to the PLD to save AC power
consumption. The CLKIN is an input to the PLD AND array and the Output Micro
Cells.
During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. The CLKIN will be disconnected
from the PLD AND array or the Micro
Cells by setting bits 4 or 5 to a “1” in PMMR0.
9.5.2.5 Input Control Signals
The PSD813F provides the option to turn off the input control signals (CNTL0-2, ALE, and
DBE) to the PLD to save AC power consumption. These control signals are inputs to the
PLD AND array. During Power Down Mode, or, if any of them are not being used as part of
the PLD logic equation, these control signals should be disabled to save AC power. They
will be disconnected from the PLD AND array by setting bits 2, 3, 4, 5, and 6 to a “1” in the
PMMR2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR33771GC-40 | Cell Rectifier Diodes |
| ZR33771GM-20 | Cell Rectifier Diodes |
| ZR33771GM-30 | Cell Rectifier Diodes |
| ZR33771GM-40 | Cell Rectifier Diodes |
| ZR33771PQC-20 | Cell Rectifier Diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
發(fā)布緊急采購，3分鐘左右您將得到回復。