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參數(shù)資料
| 型號(hào)： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 70/130頁(yè) |
| 文件大小： | 650K |
| 代理商： | ZPSD813F1V |
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PSD813F Famly
Prelimnary
66
The
PSD813F
Functional
Blocks
(cont.)
9.4.6 Port C – Functionality and Structure
Port C can be configured to perform one or more of the following functions (see Figure 29):
J
MCU I/O Mode
J
CPLD Output – McellBC[7:0] outputs can be connected to Port B or Port C.
J
CPLD Input – via the Input Micro
Cells
J
Address In – Additional high address inputs using the Input Micro
Cells.
J
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD813F device. (See Section 9.6 for more information on JTAG programming.)
J
Open Drain – Port C pins can be configured in Open Drain Mode
J
Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.
PC4 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
Port C does not support Address Out mode, and therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.
9.4.7 Port D – Functionality and Structure
Port D has three I/O pins. See Figure 30. This port does not support Address Out mode,
and therefore no Control Register is required. Port D can be configured to perform one or
more of the following functions:
J
MCU I/O Mode
J
CPLD Output – (external chip select)
J
CPLD Input – direct input to CPLD, no Input Micro
Cells
J
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
J
PD0 – ALE, as address strobe input
J
PD1 – CLKIN, as clock input to the Micro
Cells Flip Flops and APD counter
J
PD2 – CSI, as active low chip select input. A high input will disable the
Flash/EEPROM/SRAM and CSIOP.
9.4.7.1 External Chip Select
The CPLD also provides three chip select outputs on Port D pins that can be used to
select external devices. Each chip select (ECS0-2) consists of one product term that can be
configured active high or low. The output enable of the pin is controlled by either the output
enable product term or the Direction Register. (See Figure 30.)
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相關(guān)代理商/技術(shù)參數(shù) |
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| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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