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參數(shù)資料
| 型號(hào)： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 42/130頁(yè) |
| 文件大?。?/td> | 650K |
| 代理商： | ZPSD813F1V |
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PSD813F Famly
Prelimnary
38
The
PSD813F
Functional
Blocks
(cont.)
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD(DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the optional EEPROM or Flash Boot memory
(three product terms each)
1 internal SRAM select signal (two product terms)
1 internal CSIOP (PSD configuration register) select signal
1 JTAG select signal (enables JTAG on Port C)
2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD(CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and random
logic. The CPLD can also be used to generate 3 external chip selects, routed to Port D.
Although external chip selects can be produced by any Output Micro
Cell, these three
external chip selects on Port D do not consume any Output Micro
Cells.
As shown in Figure 12, the CPLD has the following blocks:
24 Input Micro
Cells (IMCs)
16 Output Micro
Cells (OMCs)
Micro
Cell Allocator
Product Term Allocator
AND array capable of generating up to 137 product terms
Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output Micro
Cells are connected to the PSD813F internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro
Cells or read data from both the Input and Output Micro
Cells.
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND logic array as required in most standard PLD macrocell
architectures.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
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