參數(shù)資料
型號: ZPSD813F1V
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲器,256K位的EEPROM,16K的位的SRAM)
文件頁數(shù): 55/130頁
文件大小: 650K
代理商: ZPSD813F1V
Prelimnary
PSD813F Famly
51
The
PSD813F
Functional
Blocks
(cont.)
Configuration
80C251
Read/Write
Pins
Connecting to
PSD813F
Pins
Page Mode
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31 compatible
A
[
7:0
]
multiplex with D
[
7:0
}
1
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A
[
7:0
]
multiplex with D
[
7:0
}
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A
[
15:8
]
multiplex with D
[
7:0
}
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A
[
15:8
]
multiplex with D
[
7:0
}
Table 19. 80C251 Configurations
9.3.5.3 80C51XA
The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that
can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are multiplexed
with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits
D[7:0].
The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 23).
The 80C51XA improves bus throughput and performance by executing Burst cycles for
code fetches. In Burst Mode, address A19-4 are latched internally by the PSD813F, while
the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access
time is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to ALE does not apply.
9.3.5.4 68HC11
Figure 24 shows an interface to a 68HC11 where the PSD813F1 is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR
signals for external devices.
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