參數(shù)資料
型號： ZPSD813F1V
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 62/130頁
文件大?。?/td> 650K
代理商： ZPSD813F1V
PSD813F Famly
Prelimnary
58
The
PSD813F
Functional
Blocks
(cont.)
Control
Register
Setting
Drection
Register
Setting
VM
Defined In
PSDabel
Defined In
PSDconfiguration
Register
Setting
JTAG
Enable
Mode
Declare
pins only
1=output,
0=input
(Note 1)
MCU I/O
NA*
0
NA
NA
PLD I/O
Logic
equations
NA
NA
(Note 1)
NA
NA
Data Port
(Port A)
NA
Specify bus type
NA
NA
NA
NA
Address Out
(Port A,B)
Declare
pins only
NA
1
1 (Note 1)
NA
NA
Address In
(Port A,B,C,D)
Logic equation
for Input
Micro
Cells
NA
NA
NA
NA
NA
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
NA
NA
NA
PIO bit =1
NA
JTAG ISP
(Note 2)
JTAGSEL
JTAG Configuration
NA
NA
NA
JTAG_
Enable
Table 21. Port Operating Mode Settings
*
NA = Not Applicable
NOTE: 1.
The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port C.
9.4.2.1 MCUI/OMode
In the MCU I/O Mode, the microcontroller uses the PSD813F ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD813F are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register, or by the output enable product term. See the subsection on
the Direction Register in the “Port Registers” section. When the pin is configured as an
output, the content of the Data Out Register drives the pin. When configured as an input,
the microcontroller can read the port input through the Data In buffer. See Figure 25.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if equation are written for them in PSDabel.
9.4.2.2 PLDI/OMode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro
Cells, and/or as an
output from the CPLD’s Output Micro
Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F1V-15J 制造商:WSI 功能描述:
ZPSD813F1V-15J-CC790 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals
ZPSD813F1V-20J 制造商:WSI 功能描述:
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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