參數(shù)資料
型號： ZPSD813F1V
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 40/130頁
文件大?。?/td> 650K
代理商： ZPSD813F1V
PSD813F Famly
Prelimnary
36
The
PSD813F
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD813F. After specifying the
logic for the PLDs using the PSDabel tool in PSDsoft, the logic is programmed into the
device and available upon power-up.
The PSD813F contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD).
The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections
9.2.1 and 9.2.2. Figure 12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal and external components, such as
memory, registers, and I/O port selects.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 Output Micro
Cells (OMCs), 24 Input Micro
Cells (IMCs), and the AND
array. The CPLD can also be used to generate external chip selects.
The AND array is used to form product terms. These product terms are specified using
PSDabel. An Input Bus consisting of 73 signals is connected to the PLDs. The signals are
shown in Table 15.
Input Source
Input Name
Number
of Signals
MCU Address Bus
MCU Control Signals
Reset
Power Down
Port A Input Micro
Cells
Port B Input Micro
Cells
Port C Input Micro
Cells
Port D Inputs
Page Register
Micro
Cell AB Feedback
Micro
Cell BC Feedback
EEPROM/Boot Flash Programming Status Bit
A[15:0]
*
CNTL[2:0]
RST
PDN
PA[7-0]
PB[7-0]
PC[7-0]
PD[2:0]
PGR(7:0)
MCELLAB.FB[7:0]
MCELLBC.FB[7:0]
Rdy/Bsy
16
3
1
1
8
8
8
3
8
8
8
1
Table 15. DPLDand CPLDInputs
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit in ZPSD813F
The PLDs in the ZPSD813F can minimize power consumption by switching off when inputs
remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off
(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turbo-off mode increases propagation delays while reducing power
consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals from
entering the PLDs. This reduces power consumption and can be used only when these
MCU control signals are not used in PLD logic equations.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F1V-15J 制造商:WSI 功能描述:
ZPSD813F1V-15J-CC790 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals
ZPSD813F1V-20J 制造商:WSI 功能描述:
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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